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From: David Gibson <david@gibson.dropbear.id.au>
To: Laurent Vivier <lvivier@redhat.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	benh@kernel.crashing.org, thuth@redhat.com, agraf@suse.de,
	mst@redhat.com, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com,
	nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com,
	abologna@redhat.com, mpolednik@redhat.com
Subject: Re: [Qemu-devel] [RFC 1/4] spapr_pci: Delegate placement of PCI host bridges to machine type
Date: Thu, 6 Oct 2016 19:11:19 +1100	[thread overview]
Message-ID: <20161006081119.GM18733@umbus.fritz.box> (raw)
In-Reply-To: <1c9498b5-469b-be4f-6a7f-f4b0e7dae4aa@redhat.com>

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On Thu, Oct 06, 2016 at 09:10:41AM +0200, Laurent Vivier wrote:
> 
> 
> On 06/10/2016 05:03, David Gibson wrote:
> > The 'spapr-pci-host-bridge' represents the virtual PCI host bridge (PHB)
> > for a PAPR guest.  Unlike on x86, it's routine on Power (both bare metal
> > and PAPR guests) to have numerous independent PHBs, each controlling a
> > separate PCI domain.
> > 
> > There are two ways of configuring the spapr-pci-host-bridge device: first
> > it can be done fully manually, specifying the locations and sizes of all
> > the IO windows.  This gives the most control, but is very awkward with 6
> > mandatory parameters.  Alternatively just an "index" can be specified
> > which essentially selects from an array of predefined PHB locations.
> > The PHB at index 0 is automatically created as the default PHB.
> > 
> > The current set of default locations causes some problems for guests with
> > large RAM (> 1 TiB) or PCI devices with very large BARs (e.g. big nVidia
> > GPGPU cards via VFIO).  Obviously, for migration we can only change the
> > locations on a new machine type, however.
> > 
> > This is awkward, because the placement is currently decided within the
> > spapr-pci-host-bridge code, so it breaks abstraction to look inside the
> > machine type version.
> > 
> > So, this patch delegates the "default mode" PHB placement from the
> > spapr-pci-host-bridge device back to the machine type via a public method
> > in sPAPRMachineClass.  It's still a bit ugly, but it's about the best we
> > can do.
> > 
> > For now, this just changes where the calculation is done.  It doesn't
> > change the actual location of the host bridges, or any other behaviour.
> > 
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> >  hw/ppc/spapr.c              | 34 ++++++++++++++++++++++++++++++++++
> >  hw/ppc/spapr_pci.c          | 22 ++++++++--------------
> >  include/hw/pci-host/spapr.h | 11 +----------
> >  include/hw/ppc/spapr.h      |  4 ++++
> >  4 files changed, 47 insertions(+), 24 deletions(-)
> > 
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index 03e3803..f6e9c2a 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -2370,6 +2370,39 @@ static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
> >      return head;
> >  }
> >  
> > +static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
> > +                                uint64_t *buid, hwaddr *pio, hwaddr *pio_size,
> > +                                hwaddr *mmio, hwaddr *mmio_size,
> > +                                unsigned n_dma, uint32_t *liobns, Error **errp)
> > +{
> > +    const uint64_t base_buid = 0x800000020000000ULL;
> > +    const hwaddr phb0_base = 0x10000000000ULL; /* 1 TiB */
> > +    const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
> > +    const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
> > +    const hwaddr pio_offset = 0x80000000; /* 2 GiB */
> > +    const uint32_t max_index = 255;
> 
> Why do you use new "const" instead of already defined "#define" from
> spapr.h?

Because the point of this change is that all the knowledge about where
the PHBis placed is supposed to be restrictedto this function.  Making
these local consts enforces that.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2016-10-06  8:11 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-06  3:03 [Qemu-devel] [RFC 0/4] Improve PCI IO window orgnaization for pseries David Gibson
2016-10-06  3:03 ` [Qemu-devel] [RFC 1/4] spapr_pci: Delegate placement of PCI host bridges to machine type David Gibson
2016-10-06  7:10   ` Laurent Vivier
2016-10-06  8:11     ` David Gibson [this message]
2016-10-06  9:36   ` Laurent Vivier
2016-10-06 23:51     ` David Gibson
2016-10-07  3:57   ` Alexey Kardashevskiy
2016-10-07  5:10     ` David Gibson
2016-10-07  5:34       ` Alexey Kardashevskiy
2016-10-07  9:17         ` David Gibson
2016-10-10  1:04           ` Alexey Kardashevskiy
2016-10-10  4:07             ` David Gibson
2016-10-11  3:17       ` David Gibson
2016-10-06  3:03 ` [Qemu-devel] [RFC 2/4] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM David Gibson
2016-10-06  7:21   ` Laurent Vivier
2016-10-06  8:46     ` David Gibson
2016-10-06  9:36   ` Laurent Vivier
2016-10-06  3:03 ` [Qemu-devel] [RFC 3/4] spapr_pci: Add a 64-bit MMIO window David Gibson
2016-10-06  3:03 ` [Qemu-devel] [RFC 4/4] spapr: Improved placement of PCI host bridges in guest memory map David Gibson
2016-10-10 15:53 ` [Qemu-devel] [RFC 0/4] Improve PCI IO window orgnaization for pseries no-reply

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