From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60836) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btcVm-00009Z-PL for qemu-devel@nongnu.org; Mon, 10 Oct 2016 11:29:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1btcVl-0008Nx-Di for qemu-devel@nongnu.org; Mon, 10 Oct 2016 11:29:06 -0400 Received: from mx1.redhat.com ([209.132.183.28]:35330) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1btcVl-0008Na-4g for qemu-devel@nongnu.org; Mon, 10 Oct 2016 11:29:05 -0400 From: =?UTF-8?q?Radim=20Kr=C4=8Dm=C3=A1=C5=99?= Date: Mon, 10 Oct 2016 17:28:43 +0200 Message-Id: <20161010152848.17902-3-rkrcmar@redhat.com> In-Reply-To: <20161010152848.17902-1-rkrcmar@redhat.com> References: <20161010152848.17902-1-rkrcmar@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v5 2/7] apic: add send_msi() to APICCommonClass List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Xu , Igor Mammedov , Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S. Tsirkin" The MMIO based interface to APIC doesn't work well with MSIs that have upper address bits set (remapped x2APIC MSIs). A specialized interface is a quick and dirty way to avoid the shortcoming. Reviewed-by: Igor Mammedov Reviewed-by: Peter Xu Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 --- v5: r-b Peter v4: r-b Igor v2: change apic_send_msi() to accept MSIMessage [Igor] --- hw/i386/kvm/apic.c | 19 +++++++++++++------ hw/i386/xen/xen_apic.c | 6 ++++++ hw/intc/apic.c | 8 ++++++-- include/hw/i386/apic_internal.h | 4 ++++ 4 files changed, 29 insertions(+), 8 deletions(-) diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index c016e63fc2ba..be55102c00ca 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -169,6 +169,17 @@ static void kvm_apic_external_nmi(APICCommonState *s= ) run_on_cpu(CPU(s->cpu), do_inject_external_nmi, s); } =20 +static void kvm_send_msi(MSIMessage *msg) +{ + int ret; + + ret =3D kvm_irqchip_send_msi(kvm_state, *msg); + if (ret < 0) { + fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n", + strerror(-ret)); + } +} + static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr, unsigned size) { @@ -179,13 +190,8 @@ static void kvm_apic_mem_write(void *opaque, hwaddr = addr, uint64_t data, unsigned size) { MSIMessage msg =3D { .address =3D addr, .data =3D data }; - int ret; =20 - ret =3D kvm_irqchip_send_msi(kvm_state, msg); - if (ret < 0) { - fprintf(stderr, "KVM: injection failed, MSI lost (%s)\n", - strerror(-ret)); - } + kvm_send_msi(&msg); } =20 static const MemoryRegionOps kvm_apic_io_ops =3D { @@ -232,6 +238,7 @@ static void kvm_apic_class_init(ObjectClass *klass, v= oid *data) k->enable_tpr_reporting =3D kvm_apic_enable_tpr_reporting; k->vapic_base_update =3D kvm_apic_vapic_base_update; k->external_nmi =3D kvm_apic_external_nmi; + k->send_msi =3D kvm_send_msi; } =20 static const TypeInfo kvm_apic_info =3D { diff --git a/hw/i386/xen/xen_apic.c b/hw/i386/xen/xen_apic.c index 21d68ee04b0a..55769eba7ede 100644 --- a/hw/i386/xen/xen_apic.c +++ b/hw/i386/xen/xen_apic.c @@ -68,6 +68,11 @@ static void xen_apic_external_nmi(APICCommonState *s) { } =20 +static void xen_send_msi(MSIMessage *msi) +{ + xen_hvm_inject_msi(msi->address, msi->data); +} + static void xen_apic_class_init(ObjectClass *klass, void *data) { APICCommonClass *k =3D APIC_COMMON_CLASS(klass); @@ -78,6 +83,7 @@ static void xen_apic_class_init(ObjectClass *klass, voi= d *data) k->get_tpr =3D xen_apic_get_tpr; k->vapic_base_update =3D xen_apic_vapic_base_update; k->external_nmi =3D xen_apic_external_nmi; + k->send_msi =3D xen_send_msi; } =20 static const TypeInfo xen_apic_info =3D { diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 7bd1d279c463..fe15fb602473 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -740,8 +740,10 @@ static uint32_t apic_mem_readl(void *opaque, hwaddr = addr) return val; } =20 -static void apic_send_msi(hwaddr addr, uint32_t data) +static void apic_send_msi(MSIMessage *msi) { + uint64_t addr =3D msi->address; + uint32_t data =3D msi->data; uint8_t dest =3D (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_= SHIFT; uint8_t vector =3D (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_= SHIFT; uint8_t dest_mode =3D (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1; @@ -762,7 +764,8 @@ static void apic_mem_writel(void *opaque, hwaddr addr= , uint32_t val) * APIC is connected directly to the CPU. * Mapping them on the global bus happens to work because * MSI registers are reserved in APIC MMIO and vice versa. */ - apic_send_msi(addr, val); + MSIMessage msi =3D { .address =3D addr, .data =3D val }; + apic_send_msi(&msi); return; } =20 @@ -913,6 +916,7 @@ static void apic_class_init(ObjectClass *klass, void = *data) k->external_nmi =3D apic_external_nmi; k->pre_save =3D apic_pre_save; k->post_load =3D apic_post_load; + k->send_msi =3D apic_send_msi; } =20 static const TypeInfo apic_info =3D { diff --git a/include/hw/i386/apic_internal.h b/include/hw/i386/apic_inter= nal.h index 286684857e9f..cdd11fb0938f 100644 --- a/include/hw/i386/apic_internal.h +++ b/include/hw/i386/apic_internal.h @@ -146,6 +146,10 @@ typedef struct APICCommonClass void (*pre_save)(APICCommonState *s); void (*post_load)(APICCommonState *s); void (*reset)(APICCommonState *s); + /* send_msi emulates an APIC bus and its proper place would be in a = new + * device, but it's convenient to have it here for now. + */ + void (*send_msi)(MSIMessage *msi); } APICCommonClass; =20 struct APICCommonState { --=20 2.10.1