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Date: Wed, 12 Oct 2016 17:55:27 -0400
From: "Emilio G. Cota" <cota@braap.org>
Message-ID: <20161012215527.GA8852@flamenco>
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Subject: Re: [Qemu-devel] MTTCG memory ordering
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To: Stefan Hajnoczi <stefanha@gmail.com>
Cc: pranith kumar <bobby.prani@gmail.com>, Alex =?iso-8859-1?Q?Benn=E9e?= <alex.bennee@linaro.org>, qemu-devel <qemu-devel@nongnu.org>, Richard Henderson <rth@twiddle.net>

On Wed, Oct 12, 2016 at 10:58:43 +0200, Stefan Hajnoczi wrote:
> Hi Pranith,
> I was curious about the status of your MTTCG GSoC work:
> 
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the case where a strong target is emulated on a weak host.
> 
> Did you make TCG automatically emit barriers so stronger targets (x86)
> run correctly on weaker targets (ARM)?

Here are some numbers on this. Chart:
  http://imgur.com/a/H9E9R

The overhead of emitting barriers all over the place is significant
(~3x for integer code), but that's the price of correctness as
the ArMOR paper shows[*] (this is the SYNC option in the chart).

A faster alternative also provided by ArMOR is to pretend the host
isn't multi-copy atomic (i.e. the iriw litmus test would fail); this
is the PowerA option in the chart.

An even better alternative is to let the hardware deal with this.
Unfortunately, so far only recent IBM processors support this
(the feature is called Strong Access Ordering--SAO in the chart).

[*] ArMOR: Defending Against Memory Consistency Model Mismatches
    in Heterogeneous Architectures
  http://www.cs.princeton.edu/~ctrippel/dlustig_ISCA15.pdf

		Emilio