[Qemu-devel] MTTCG memory ordering

[Qemu-devel] MTTCG memory ordering

[Stefan Hajnoczi]

Hi Pranith,
I was curious about the status of your MTTCG GSoC work:

I saw your fence series which implements the noop memory barrier/fence
instructions on various architectures, but I wasn't sure if that also
covers the case where a strong target is emulated on a weak host.

Did you make TCG automatically emit barriers so stronger targets (x86)
run correctly on weaker targets (ARM)?

Thanks,
Stefan

Re: [Qemu-devel] MTTCG memory ordering

[Laszlo Ersek]

On 10/12/16 10:58, Stefan Hajnoczi wrote:
> Hi Pranith,
> I was curious about the status of your MTTCG GSoC work:
> 
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the case where a strong target is emulated on a weak host.
> 
> Did you make TCG automatically emit barriers so stronger targets (x86)
> run correctly on weaker targets (ARM)?

(Testing that might run into other problems:
<https://bugs.launchpad.net/qemu/+bug/893208/>)

Re: [Qemu-devel] MTTCG memory ordering

[Pranith Kumar]

Hi Stefan,

Stefan Hajnoczi writes:

> Hi Pranith,
> I was curious about the status of your MTTCG GSoC work:
>
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the case where a strong target is emulated on a weak host.
>

No, this work is still pending. The current implementation only supports weak
on strong (the simplest case) by emitting barriers explicitly.

> Did you make TCG automatically emit barriers so stronger targets (x86)
> run correctly on weaker targets (ARM)?

We did consider doing this by emitting barriers implicitly for each memory
instruction of a strong target but decided that it would be too costly. There
is, AFAIK, no trivial solution to avoiding this overhead as of now.

I will start working on this next step soon, once I finish the tcg test setup.

Thanks,
-- 
Pranith

Re: [Qemu-devel] MTTCG memory ordering

[Emilio G. Cota]

On Wed, Oct 12, 2016 at 10:58:43 +0200, Stefan Hajnoczi wrote:
> Hi Pranith,
> I was curious about the status of your MTTCG GSoC work:
> 
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the case where a strong target is emulated on a weak host.
> 
> Did you make TCG automatically emit barriers so stronger targets (x86)
> run correctly on weaker targets (ARM)?

Here are some numbers on this. Chart:
  http://imgur.com/a/H9E9R

The overhead of emitting barriers all over the place is significant
(~3x for integer code), but that's the price of correctness as
the ArMOR paper shows[*] (this is the SYNC option in the chart).

A faster alternative also provided by ArMOR is to pretend the host
isn't multi-copy atomic (i.e. the iriw litmus test would fail); this
is the PowerA option in the chart.

An even better alternative is to let the hardware deal with this.
Unfortunately, so far only recent IBM processors support this
(the feature is called Strong Access Ordering--SAO in the chart).

[*] ArMOR: Defending Against Memory Consistency Model Mismatches
    in Heterogeneous Architectures
  http://www.cs.princeton.edu/~ctrippel/dlustig_ISCA15.pdf

		Emilio

Re: [Qemu-devel] MTTCG memory ordering

[Stefan Hajnoczi]

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On Wed, Oct 12, 2016 at 10:58:43AM +0200, Stefan Hajnoczi wrote:
> I was curious about the status of your MTTCG GSoC work:
> 
> I saw your fence series which implements the noop memory barrier/fence
> instructions on various architectures, but I wasn't sure if that also
> covers the case where a strong target is emulated on a weak host.
> 
> Did you make TCG automatically emit barriers so stronger targets (x86)
> run correctly on weaker targets (ARM)?

Thanks for the responses!

I'm putting together 3 minutes of slides to present at the Google Summer
of Code Mentor Summit.  This project is a good example of the technical
challenges in QEMU so I wanted to showcase it.

Glad I asked for clarification because originally I thought this project
was about emulating strong on weak memory ordering :).

Stefan

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