From: David Gibson <david@gibson.dropbear.id.au>
To: Laurent Vivier <lvivier@redhat.com>
Cc: agraf@suse.de, mst@redhat.com,
Andrea Bolognani <abologna@redhat.com>,
aik@ozlabs.ru, qemu-devel@nongnu.org, qemu-ppc@nongnu.org,
mdroth@linux.vnet.ibm.com, benh@kernel.crashing.org
Subject: Re: [Qemu-devel] [PATCHv2 4/7] spapr_pci: Delegate placement of PCI host bridges to machine type
Date: Thu, 13 Oct 2016 10:25:04 +1100 [thread overview]
Message-ID: <20161012232504.GB18039@umbus.fritz.box> (raw)
In-Reply-To: <376499b1-5464-a89a-d4d4-b031c8fbc9bd@redhat.com>
[-- Attachment #1: Type: text/plain, Size: 4417 bytes --]
On Wed, Oct 12, 2016 at 11:26:05AM +0200, Laurent Vivier wrote:
>
>
> On 12/10/2016 06:44, David Gibson wrote:
> > The 'spapr-pci-host-bridge' represents the virtual PCI host bridge (PHB)
> > for a PAPR guest. Unlike on x86, it's routine on Power (both bare metal
> > and PAPR guests) to have numerous independent PHBs, each controlling a
> > separate PCI domain.
> >
> > There are two ways of configuring the spapr-pci-host-bridge device: first
> > it can be done fully manually, specifying the locations and sizes of all
> > the IO windows. This gives the most control, but is very awkward with 6
> > mandatory parameters. Alternatively just an "index" can be specified
> > which essentially selects from an array of predefined PHB locations.
> > The PHB at index 0 is automatically created as the default PHB.
> >
> > The current set of default locations causes some problems for guests with
> > large RAM (> 1 TiB) or PCI devices with very large BARs (e.g. big nVidia
> > GPGPU cards via VFIO). Obviously, for migration we can only change the
> > locations on a new machine type, however.
> >
> > This is awkward, because the placement is currently decided within the
> > spapr-pci-host-bridge code, so it breaks abstraction to look inside the
> > machine type version.
> >
> > So, this patch delegates the "default mode" PHB placement from the
> > spapr-pci-host-bridge device back to the machine type via a public method
> > in sPAPRMachineClass. It's still a bit ugly, but it's about the best we
> > can do.
> >
> > For now, this just changes where the calculation is done. It doesn't
> > change the actual location of the host bridges, or any other behaviour.
> >
> > Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
> > ---
> > hw/ppc/spapr.c | 34 ++++++++++++++++++++++++++++++++++
> > hw/ppc/spapr_pci.c | 22 ++++++++--------------
> > include/hw/pci-host/spapr.h | 11 +----------
> > include/hw/ppc/spapr.h | 4 ++++
> > 4 files changed, 47 insertions(+), 24 deletions(-)
> >
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index 03e3803..f6e9c2a 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -2370,6 +2370,39 @@ static HotpluggableCPUList *spapr_query_hotpluggable_cpus(MachineState *machine)
> > return head;
> > }
> >
> > +static void spapr_phb_placement(sPAPRMachineState *spapr, uint32_t index,
> > + uint64_t *buid, hwaddr *pio, hwaddr *pio_size,
> > + hwaddr *mmio, hwaddr *mmio_size,
> > + unsigned n_dma, uint32_t *liobns, Error **errp)
> > +{
> > + const uint64_t base_buid = 0x800000020000000ULL;
> > + const hwaddr phb0_base = 0x10000000000ULL; /* 1 TiB */
> > + const hwaddr phb_spacing = 0x1000000000ULL; /* 64 GiB */
> > + const hwaddr mmio_offset = 0xa0000000; /* 2 GiB + 512 MiB */
> > + const hwaddr pio_offset = 0x80000000; /* 2 GiB */
> > + const uint32_t max_index = 255;
> > +
> > + hwaddr phb_base;
> > + int i;
> > +
> > + if (index > max_index) {
> > + error_setg(errp, "\"index\" for PAPR PHB is too large (max %u)",
> > + max_index);
> > + return;
> > + }
> > +
> > + *buid = base_buid + index;
> > + for (i = 0; i < n_dma; ++i) {
> > + liobns[i] = SPAPR_PCI_LIOBN(index, i);
> > + }
> > +
> > + phb_base = phb0_base + index * phb_spacing;
> > + *pio = phb_base + pio_offset;
> > + *pio_size = SPAPR_PCI_IO_WIN_SIZE;
> > + *mmio = phb_base + mmio_offset;
> > + *mmio_size = SPAPR_PCI_MMIO_WIN_SIZE;
>
> sphb->io_win_size (*pio_size) and sphb->mem_win_size (*mmio_size) were
> previously initialized from spapr_phb_properties[], you overwrite these
> values now. Is this what you want?
Uuuhhhh... I guess not.
I put the sizes in here because I wanted to have all the configuration
for the common case in one place, rather than split between
phb_placement() and the default properties.
But you're right, it does introduce a real, if small, behaviour
change, which this patch isn't supposed to do. I'll change it.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
next prev parent reply other threads:[~2016-10-12 23:55 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-12 4:44 [Qemu-devel] [PATCHv2 0/7] Improve PCI IO window orgnaization for pseries David Gibson
2016-10-12 4:44 ` [Qemu-devel] [PATCHv2 1/7] libqos: Isolate knowledge of spapr memory map to qpci_init_spapr() David Gibson
2016-10-12 8:00 ` Laurent Vivier
2016-10-12 4:44 ` [Qemu-devel] [PATCHv2 2/7] libqos: Correct error in PCI hole sizing for spapr David Gibson
2016-10-12 8:07 ` Laurent Vivier
2016-10-12 4:44 ` [Qemu-devel] [PATCHv2 3/7] libqos: Limit spapr-pci to 32-bit MMIO for now David Gibson
2016-10-12 8:20 ` Laurent Vivier
2016-10-12 4:44 ` [Qemu-devel] [PATCHv2 4/7] spapr_pci: Delegate placement of PCI host bridges to machine type David Gibson
2016-10-12 9:26 ` Laurent Vivier
2016-10-12 23:25 ` David Gibson [this message]
2016-10-12 4:44 ` [Qemu-devel] [PATCHv2 5/7] spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM David Gibson
2016-10-12 10:07 ` Laurent Vivier
2016-10-12 10:55 ` David Gibson
2016-10-12 12:06 ` Laurent Vivier
2016-10-12 23:48 ` David Gibson
2016-10-12 4:44 ` [Qemu-devel] [PATCHv2 6/7] spapr_pci: Add a 64-bit MMIO window David Gibson
2016-10-12 13:39 ` Laurent Vivier
2016-10-12 4:44 ` [Qemu-devel] [PATCHv2 7/7] spapr: Improved placement of PCI host bridges in guest memory map David Gibson
2016-10-12 8:26 ` [Qemu-devel] [PATCHv2 0/7] Improve PCI IO window orgnaization for pseries no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20161012232504.GB18039@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=abologna@redhat.com \
--cc=agraf@suse.de \
--cc=aik@ozlabs.ru \
--cc=benh@kernel.crashing.org \
--cc=lvivier@redhat.com \
--cc=mdroth@linux.vnet.ibm.com \
--cc=mst@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).