From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38016) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buYMz-000547-SS for qemu-devel@nongnu.org; Thu, 13 Oct 2016 01:15:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1buYMx-00086t-Ci for qemu-devel@nongnu.org; Thu, 13 Oct 2016 01:15:53 -0400 Date: Thu, 13 Oct 2016 13:58:23 +1100 From: David Gibson Message-ID: <20161013025823.GN18039@umbus.fritz.box> References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-10-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="tpyx7gKuSYt+mjHM" Content-Disposition: inline In-Reply-To: <1475479496-16158-10-git-send-email-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH v4 09/20] ppc/pnv: add a ISA bus List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org --tpyx7gKuSYt+mjHM Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 03, 2016 at 09:24:45AM +0200, C=E9dric Le Goater wrote: > As Qemu only supports a single instance of the ISA bus, we use the LPC > controller of chip 0 to create one and plug in a couple of useful > devices, like an UART and RTC. An IPMI BT device, which is also an ISA > device, can be defined on the command line to connect an external BMC. > That is for later. >=20 > The PowerNV machine now has a console. Skiboot should load a kernel > and jump into it but execution will stop quite early because we lack a > model for the native XICS controller for the moment : >=20 > [ 0.000000] NR_IRQS:512 nr_irqs:512 16 > [ 0.000000] XICS: Cannot find a Presentation Controller ! > [ 0.000000] ------------[ cut here ]------------ > [ 0.000000] WARNING: at arch/powerpc/platforms/powernv/setup.c:81 > ... > [ 0.000000] NIP [c00000000079d65c] pnv_init_IRQ+0x30/0x44 >=20 > You can still do a few things under xmon. >=20 > Based on previous work from : > Benjamin Herrenschmidt >=20 > Signed-off-by: C=E9dric Le Goater Reviewed-by: David Gibson > --- > hw/ppc/pnv.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++= ++++++ > include/hw/ppc/pnv.h | 2 ++ > 2 files changed, 67 insertions(+) >=20 > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index e41244294435..4a71b18bf38b 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -34,6 +34,10 @@ > =20 > #include "hw/ppc/pnv_xscom.h" > =20 > +#include "hw/isa/isa.h" > +#include "hw/char/serial.h" > +#include "hw/timer/mc146818rtc.h" > + > #include > =20 > #define FDT_MAX_SIZE 0x00100000 > @@ -302,6 +306,58 @@ static void ppc_powernv_reset(void) > cpu_physical_memory_write(POWERNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); > } > =20 > +/* If we don't use the built-in LPC interrupt deserializer, we need > + * to provide a set of qirqs for the ISA bus or things will go bad. > + * > + * Most machines using pre-Naples chips (without said deserializer) > + * have a CPLD that will collect the SerIRQ and shoot them as a > + * single level interrupt to the P8 chip. So let's setup a hook > + * for doing just that. > + * > + * Note: The actual interrupt input isn't emulated yet, this will > + * come with the PSI bridge model. > + */ > +static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) > +{ > + /* We don't yet emulate the PSI bridge which provides the external > + * interrupt, so just drop interrupts on the floor > + */ > +} > + > +static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) > +{ > + /* XXX TODO */ > +} > + > +static ISABus *pnv_isa_create(PnvChip *chip) > +{ > + PnvLpcController *lpc =3D &chip->lpc; > + ISABus *isa_bus; > + qemu_irq *irqs; > + PnvChipClass *pcc =3D PNV_CHIP_GET_CLASS(chip); > + > + /* let isa_bus_new() create its own bridge on SysBus otherwise > + * devices speficied on the command line won't find the bus and > + * will fail to create. > + */ > + isa_bus =3D isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, > + &error_fatal); > + > + /* Not all variants have a working serial irq decoder. If not, > + * handling of LPC interrupts becomes a platform issue (some > + * platforms have a CPLD to do it). > + */ > + if (pcc->chip_type =3D=3D PNV_CHIP_POWER8NVL) { > + irqs =3D qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, ISA_NU= M_IRQS); > + } else { > + irqs =3D qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, NULL, > + ISA_NUM_IRQS); > + } > + > + isa_bus_irqs(isa_bus, irqs); > + return isa_bus; > +} > + > static void ppc_powernv_init(MachineState *machine) > { > PnvMachineState *pnv =3D POWERNV_MACHINE(machine); > @@ -390,6 +446,15 @@ static void ppc_powernv_init(MachineState *machine) > object_property_set_bool(chip, true, "realized", &error_fatal); > } > g_free(chip_typename); > + > + /* Instantiate ISA bus on chip 0 */ > + pnv->isa_bus =3D pnv_isa_create(pnv->chips[0]); > + > + /* Create serial port */ > + serial_hds_isa_init(pnv->isa_bus, MAX_SERIAL_PORTS); > + > + /* Create an RTC ISA device too */ > + rtc_init(pnv->isa_bus, 2000, NULL); > } > =20 > /* > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index e586ff4e735e..617c3fdd4f06 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -110,6 +110,8 @@ typedef struct PnvMachineState { > =20 > uint32_t num_chips; > PnvChip **chips; > + > + ISABus *isa_bus; > } PnvMachineState; > =20 > #define POWERNV_FDT_ADDR 0x01000000 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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