From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53773) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bup4y-00037u-2A for qemu-devel@nongnu.org; Thu, 13 Oct 2016 19:06:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bup4t-0001kd-7S for qemu-devel@nongnu.org; Thu, 13 Oct 2016 19:06:22 -0400 Date: Fri, 14 Oct 2016 09:24:57 +1100 From: David Gibson Message-ID: <20161013222457.GO18039@umbus.fritz.box> References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-8-git-send-email-clg@kaod.org> <20161013005118.GI18039@umbus.fritz.box> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="V7BlxAaPrdhzdIM1" Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCH v4 07/20] ppc/pnv: add XSCOM handlers to PnvCore List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org --V7BlxAaPrdhzdIM1 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Oct 13, 2016 at 08:50:41AM +0200, C=E9dric Le Goater wrote: > On 10/13/2016 02:51 AM, David Gibson wrote: > > On Mon, Oct 03, 2016 at 09:24:43AM +0200, C=E9dric Le Goater wrote: > >> Now that we are using real HW ids for the cores in PowerNV chips, we > >> can route the XSCOM accesses to them. We just need to attach a > >> specific XSCOM memory region to each core in the appropriate window > >> for the core number. > >> > >> To start with, let's install the DTS (Digital Thermal Sensor) handlers > >> which should return 38=B0C for each core. > >> > >> Signed-off-by: C=E9dric Le Goater > >> --- > >> > >> Changes since v3: > >> > >> - moved to new XSCOM model > >> - kept the write op on the XSCOM memory region for later use > >> > >> Changes since v2: > >> > >> - added a XSCOM memory region to handle access to the EX core > >> registers =20 > >> - extended the PnvCore object with a XSCOM_INTERFACE so that we can > >> use pnv_xscom_pcba() and pnv_xscom_addr() to handle XSCOM address > >> translation. > >> > >> hw/ppc/pnv.c | 4 ++++ > >> hw/ppc/pnv_core.c | 50 +++++++++++++++++++++++++++++++++++++= +++++++++ > >> include/hw/ppc/pnv_core.h | 2 ++ > >> include/hw/ppc/pnv_xscom.h | 19 ++++++++++++++++++ > >> 4 files changed, 75 insertions(+) > >> > >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > >> index 5e19b6880387..ffe245fe59d2 100644 > >> --- a/hw/ppc/pnv.c > >> +++ b/hw/ppc/pnv.c > >> @@ -620,6 +620,10 @@ static void pnv_chip_realize(DeviceState *dev, Er= ror **errp) > >> &error_fatal); > >> object_unref(OBJECT(pnv_core)); > >> i++; > >> + > >> + memory_region_add_subregion(&chip->xscom, > >> + PNV_XSCOM_EX_CORE_BASE(core_hwid) << 3, > >> + &PNV_CORE(pnv_core)->xscom_regs); > >=20 > > Might be worth adding some convenience functions for doing the various > > bits of xscom MR juggling, otherwise this looks fine. >=20 > To do the 8 byte shifting ? or something like this : > =20 > void pnv_xscom_add_subregion(PnvChip *chip, uint32_t pcba, > MemoryRegion *subregion); Yes, something like that, which incorporates the << 3. And maybe another one to construct the MR for use on the scom device side. > or even : >=20 > void pnv_xscom_add_subregion(PnvChip *chip, PnvXScomInterface *obj) >=20 > but that would require some more handlers under PnvXScomInterface. >=20 > Thanks, >=20 > C. >=20 >=20 > >> } > >> g_free(typename); > >> } > >> diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > >> index d37788f142f4..a1c8a14f06b6 100644 > >> --- a/hw/ppc/pnv_core.c > >> +++ b/hw/ppc/pnv_core.c > >> @@ -19,6 +19,7 @@ > >> #include "qemu/osdep.h" > >> #include "sysemu/sysemu.h" > >> #include "qapi/error.h" > >> +#include "qemu/log.h" > >> #include "target-ppc/cpu.h" > >> #include "hw/ppc/ppc.h" > >> #include "hw/ppc/pnv.h" > >> @@ -64,6 +65,51 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error= **errp) > >> powernv_cpu_reset(cpu); > >> } > >> =20 > >> +/* > >> + * These values are read by the PowerNV HW monitors under Linux > >> + */ > >> +#define PNV_XSCOM_EX_DTS_RESULT0 0x50000 > >> +#define PNV_XSCOM_EX_DTS_RESULT1 0x50001 > >> + > >> +static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr, > >> + unsigned int width) > >> +{ > >> + uint32_t offset =3D addr >> 3; > >> + uint64_t val =3D 0; > >> + > >> + /* The result should be 38 C */ > >> + switch (offset) { > >> + case PNV_XSCOM_EX_DTS_RESULT0: > >> + val =3D 0x26f024f023f0000ull; > >> + break; > >> + case PNV_XSCOM_EX_DTS_RESULT1: > >> + val =3D 0x24f000000000000ull; > >> + break; > >> + default: > >> + qemu_log_mask(LOG_UNIMP, "Warning: reading reg=3D0x%" HWADDR_= PRIx, > >> + addr); > >> + } > >> + > >> + return val; > >> +} > >> + > >> +static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t = val, > >> + unsigned int width) > >> +{ > >> + qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=3D0x%" HWADDR_P= RIx, > >> + addr); > >> +} > >> + > >> +static const MemoryRegionOps pnv_core_xscom_ops =3D { > >> + .read =3D pnv_core_xscom_read, > >> + .write =3D pnv_core_xscom_write, > >> + .valid.min_access_size =3D 8, > >> + .valid.max_access_size =3D 8, > >> + .impl.min_access_size =3D 8, > >> + .impl.max_access_size =3D 8, > >> + .endianness =3D DEVICE_BIG_ENDIAN, > >> +}; > >> + > >> static void pnv_core_realize_child(Object *child, Error **errp) > >> { > >> Error *local_err =3D NULL; > >> @@ -119,6 +165,10 @@ static void pnv_core_realize(DeviceState *dev, Er= ror **errp) > >> goto err; > >> } > >> } > >> + > >> + snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); > >> + memory_region_init_io(&pc->xscom_regs, OBJECT(dev), &pnv_core_xsc= om_ops, > >> + pc, name, PNV_XSCOM_EX_CORE_SIZE << 3); > >> return; > >> =20 > >> err: > >> diff --git a/include/hw/ppc/pnv_core.h b/include/hw/ppc/pnv_core.h > >> index a151e281c017..2955a41c901f 100644 > >> --- a/include/hw/ppc/pnv_core.h > >> +++ b/include/hw/ppc/pnv_core.h > >> @@ -36,6 +36,8 @@ typedef struct PnvCore { > >> /*< public >*/ > >> void *threads; > >> uint32_t pir; > >> + > >> + MemoryRegion xscom_regs; > >> } PnvCore; > >> =20 > >> typedef struct PnvCoreClass { > >> diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h > >> index f50eb0bc4099..79975a6cbe46 100644 > >> --- a/include/hw/ppc/pnv_xscom.h > >> +++ b/include/hw/ppc/pnv_xscom.h > >> @@ -41,6 +41,25 @@ typedef struct PnvXScomInterfaceClass { > >> int (*populate)(PnvXScomInterface *dev, void *fdt, int offset); > >> } PnvXScomInterfaceClass; > >> =20 > >> +/* > >> + * Layout of the XSCOM PCB addresses of EX core 1 > >> + * > >> + * GPIO 0x1100xxxx > >> + * SCOM 0x1101xxxx > >> + * OHA 0x1102xxxx > >> + * CLOCK CTL 0x1103xxxx > >> + * FIR 0x1104xxxx > >> + * THERM 0x1105xxxx > >> + * 0x1106xxxx > >> + * .. > >> + * 0x110Exxxx > >> + * PCB SLAVE 0x110Fxxxx > >> + */ > >> + > >> +#define PNV_XSCOM_EX_BASE 0x10000000 > >> +#define PNV_XSCOM_EX_CORE_BASE(i) (PNV_XSCOM_EX_BASE | (((uint64_t)i)= << 24)) > >> +#define PNV_XSCOM_EX_CORE_SIZE 0x100000 > >> + > >> extern void pnv_xscom_realize(PnvChip *chip, Error **errp); > >> extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset); > >> =20 > >=20 >=20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --V7BlxAaPrdhzdIM1 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYAAm2AAoJEGw4ysog2bOSmMgP/2sXr/Sb7uoZFm+1JACJdX0f 1TQnRnmaqBwUbh4qMj35qCoMW3Vny9Bxzbcqk5uo+aPQSYBIsu7mOHLixzGHf7Yh wN0e4LCmwLt6lOONIrElubUL6yhjvSF9lI66EJF+ovYPkt64X9KKiyoR+MwxZWXu ule+fRKzqFlQ95AXDl6Y3XNnvWe064cMl5N8YbpJIDttWHft/5z0c4e9vjNhtz+E RB+Ylsb43x5/mNXgAO4HuWKymoFZ7hW4MuAi8rS5st3i+Nvy0bOnuQ6KpctwnFz1 XRVRdGT5W+0/z5aMw76Vb/LRPlex2YR0/5C2ijquyAoDUDALDCTjClLo03mPeYBQ 9gI9BZyrHZSfOI+uYzU3JPCEOvBwdVYixYC23nkgPPNiYtO3AU3CeFcb4jLBuHbR SeqB8V+iPBY774hi+Z61vY8nQ7+EySPmkSzenkLez6LcJgIvNGGSjJuGjk+kaDTN ChCoynCPcKmpoHG+zFfcQIfmcmrqOjQG8SvkQjzhG2AAAEibrfnIdezas/ilQgkv i2U2Ns7Vw6We6sz45B5O7vGc8VvpYdY+EsS9tWVAd8M0i+f1i2vogGyEhuGRk4DD xFp3T/fVlIsq1vTApjA/2il91u4XLIoaTtwjVjrSuPS31MtTff4HE+AftHQ0lUCE Bg7ZdUJyR/heieBhbXOs =wvre -----END PGP SIGNATURE----- --V7BlxAaPrdhzdIM1--