From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buwWT-0002CV-Li for qemu-devel@nongnu.org; Fri, 14 Oct 2016 03:03:19 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1buwWR-0005EH-SE for qemu-devel@nongnu.org; Fri, 14 Oct 2016 03:03:17 -0400 Date: Fri, 14 Oct 2016 17:18:16 +1100 From: David Gibson Message-ID: <20161014061816.GR28562@umbus> References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-17-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="jTlsQtO0VwrbBARu" Content-Disposition: inline In-Reply-To: <1475479496-16158-17-git-send-email-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH v4 16/20] ppc/pnv: add a XICS native to each PowerNV chip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org --jTlsQtO0VwrbBARu Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 03, 2016 at 09:24:52AM +0200, C=E9dric Le Goater wrote: > and also link the XICS object to each core as it is needed to do the > CPU setup. >=20 > Signed-off-by: C=E9dric Le Goater > --- > hw/ppc/pnv.c | 18 ++++++++++++++++++ > hw/ppc/pnv_core.c | 25 +++++++++++++++++++++---- > include/hw/ppc/pnv.h | 2 ++ > 3 files changed, 41 insertions(+), 4 deletions(-) >=20 > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 4a71b18bf38b..6335ca11efe7 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -32,6 +32,7 @@ > #include "exec/address-spaces.h" > #include "qemu/cutils.h" > =20 > +#include "hw/ppc/xics.h" > #include "hw/ppc/pnv_xscom.h" > =20 > #include "hw/isa/isa.h" > @@ -223,6 +224,7 @@ static void powernv_populate_chip(PnvChip *chip, void= *fdt) > char *typename =3D pnv_core_typename(pcc->cpu_model); > size_t typesize =3D object_type_get_instance_size(typename); > int i; > + int smt =3D 1; /* TCG does not support more for the moment */ > =20 > pnv_xscom_populate(chip, fdt, 0); > =20 > @@ -230,6 +232,9 @@ static void powernv_populate_chip(PnvChip *chip, void= *fdt) > PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); > =20 > powernv_create_core_node(chip, pnv_core, fdt); > + > + /* Interrupt presentation controllers (ICP). One per core. */ > + xics_native_populate_icp(chip, fdt, 0, pnv_core->pir, smt); > } > =20 > /* Put all the memory in one node on chip 0 until we find a way to > @@ -631,6 +636,9 @@ static void pnv_chip_init(Object *obj) > =20 > object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); > object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); > + > + object_initialize(&chip->xics, sizeof(chip->xics), TYPE_XICS_NATIVE); > + object_property_add_child(obj, "xics", OBJECT(&chip->xics), NULL); > } > =20 > static void pnv_chip_realize(DeviceState *dev, Error **errp) > @@ -641,6 +649,7 @@ static void pnv_chip_realize(DeviceState *dev, Error = **errp) > char *typename =3D pnv_core_typename(pcc->cpu_model); > size_t typesize =3D object_type_get_instance_size(typename); > int i, core_hwid; > + int smt =3D 1; /* TCG does not support more for the moment */ > =20 > if (!object_class_by_name(typename)) { > error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typenam= e); > @@ -662,6 +671,13 @@ static void pnv_chip_realize(DeviceState *dev, Error= **errp) > return; > } > =20 > + /* Set up Interrupt Controller before we create the VCPUs */ > + object_property_set_int(OBJECT(&chip->xics), smp_cpus * smt / smp_th= reads, > + "nr_servers", &error_fatal); / smp_threads doesn't look right (more actual threads means less servers). I think you just want smp_cpus * smp_threads. Or actually cores_per_chip * smp_threads. > + object_property_set_bool(OBJECT(&chip->xics), true, "realized", > + &error_fatal); > + sysbus_mmio_map(SYS_BUS_DEVICE(&chip->xics), 0, PNV_XICS_BASE); > + > chip->cores =3D g_malloc0(typesize * chip->nr_cores); > =20 > for (i =3D 0, core_hwid =3D 0; (core_hwid < sizeof(chip->cores_mask)= * 8) > @@ -684,6 +700,8 @@ static void pnv_chip_realize(DeviceState *dev, Error = **errp) > object_property_set_int(OBJECT(pnv_core), > pcc->core_pir(chip, core_hwid), > "pir", &error_fatal); > + object_property_add_const_link(OBJECT(pnv_core), "xics", > + OBJECT(&chip->xics), &error_fatal= ); > object_property_set_bool(OBJECT(pnv_core), true, "realized", > &error_fatal); > object_unref(OBJECT(pnv_core)); > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > index a1c8a14f06b6..fe18e3150f78 100644 > --- a/hw/ppc/pnv_core.c > +++ b/hw/ppc/pnv_core.c > @@ -24,6 +24,7 @@ > #include "hw/ppc/ppc.h" > #include "hw/ppc/pnv.h" > #include "hw/ppc/pnv_core.h" > +#include "hw/ppc/xics.h" > =20 > static void powernv_cpu_reset(void *opaque) > { > @@ -54,7 +55,7 @@ static void powernv_cpu_reset(void *opaque) > env->msr |=3D MSR_HVB; /* Hypervisor mode */ > } > =20 > -static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp) > +static void powernv_cpu_init(PowerPCCPU *cpu, XICSState *xics, Error **e= rrp) > { > CPUPPCState *env =3D &cpu->env; > =20 > @@ -63,6 +64,12 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **= errp) > =20 > qemu_register_reset(powernv_cpu_reset, cpu); > powernv_cpu_reset(cpu); > + > + /* > + * XICS native cpu_setup() expects SPR_PIR to be set. So it needs > + * to run after powernv_cpu_reset() > + */ > + xics_cpu_setup(xics, cpu); > } > =20 > /* > @@ -110,7 +117,7 @@ static const MemoryRegionOps pnv_core_xscom_ops =3D { > .endianness =3D DEVICE_BIG_ENDIAN, > }; > =20 > -static void pnv_core_realize_child(Object *child, Error **errp) > +static void pnv_core_realize_child(Object *child, XICSState *xics, Error= **errp) > { > Error *local_err =3D NULL; > CPUState *cs =3D CPU(child); > @@ -122,7 +129,7 @@ static void pnv_core_realize_child(Object *child, Err= or **errp) > return; > } > =20 > - powernv_cpu_init(cpu, &local_err); > + powernv_cpu_init(cpu, xics, &local_err); > if (local_err) { > error_propagate(errp, local_err); > return; > @@ -140,6 +147,7 @@ static void pnv_core_realize(DeviceState *dev, Error = **errp) > void *obj; > int i, j; > char name[32]; > + XICSState *xics; > =20 > pc->threads =3D g_malloc0(size * cc->nr_threads); > for (i =3D 0; i < cc->nr_threads; i++) { > @@ -157,10 +165,19 @@ static void pnv_core_realize(DeviceState *dev, Erro= r **errp) > object_unref(obj); > } > =20 > + /* get XICS object from chip */ > + obj =3D object_property_get_link(OBJECT(dev), "xics", &local_err); > + if (!obj) { > + error_setg(errp, "%s: required link 'xics' not found: %s", > + __func__, error_get_pretty(local_err)); > + return; > + } > + xics =3D XICS_COMMON(obj); > + > for (j =3D 0; j < cc->nr_threads; j++) { > obj =3D pc->threads + j * size; > =20 > - pnv_core_realize_child(obj, &local_err); > + pnv_core_realize_child(obj, xics, &local_err); > if (local_err) { > goto err; > } > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 3f24b87d199b..73d26c55d993 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -23,6 +23,7 @@ > #include "hw/sysbus.h" > #include "hw/ppc/pnv_xscom.h" > #include "hw/ppc/pnv_lpc.h" > +#include "hw/ppc/xics.h" > =20 > #define TYPE_PNV_CHIP "powernv-chip" > #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) > @@ -55,6 +56,7 @@ typedef struct PnvChip { > void *cores; > =20 > PnvLpcController lpc; > + XICSNative xics; > } PnvChip; > =20 > typedef struct PnvChipClass { --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --jTlsQtO0VwrbBARu Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYAHinAAoJEGw4ysog2bOSR4YQALRtKX2LH+CRve6X7KNF3468 TuDzjhJe1V8cr4d9cob+z15yh4i+UUEVQRjR78OW2F5gxacUdbeGF/qJJr/55kNZ I7lKN+ugTsWNcLmMF8oTTr6JurJYqiYvFJVs5PVn9foey4eOMg8iHImb3l3lyIjU tEgQ0gN6ohxzwOE4WMcsiV0Yz65ZlZG/A0kX8up5LBtrL/FC4vGi71Z10Bsm4qxH 8GNs5J6pokyueF2xei8UmuMt8YH7O/ObIe4C2YGQve2Td/vDFAGq+XffWUY+ekk2 0f4jsaW+4cVyBjLcVD9ckgbugbS84+R2Z88NcHi1L+OYCtvtZzmhqNCNDnML0g0V 3g5rVgsNQCo0MtGEVbTvNuE/5pigk7giIX+YeqrIwbk0IxSek/2c3O8has4KX2CI wMJE5R7AplIA9Q+yWiziWtg9FFq+iWu2eRO9mz3P1e/u5ZxZ5hx/nTG+OYybzupo RgkqGnSoGmlGsKhVTVtpuACw2DZj12v2F8f+c9YRjAytpY8RoW2nNCVD1yWumYtu vSPvL5TcBiYBXO5qdSLHeBSsSHWI8Nr1+l809sQEAepWZ5t7mUqscUmal3Ifxqln nt/Ez/ARQbtWtf5unD9AtvHGFWUMVlWvJGoTTc0oFk9V9Bqkr5AnEQ/D15TgyJUi af4k1SYC9PXyv7b3+ng+ =0GzL -----END PGP SIGNATURE----- --jTlsQtO0VwrbBARu--