From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44038) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1buwWV-0002Cb-3P for qemu-devel@nongnu.org; Fri, 14 Oct 2016 03:03:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1buwWS-0005Et-RA for qemu-devel@nongnu.org; Fri, 14 Oct 2016 03:03:18 -0400 Date: Fri, 14 Oct 2016 17:34:01 +1100 From: David Gibson Message-ID: <20161014063401.GT28562@umbus> References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-19-git-send-email-clg@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="EmW68jKGQIhj8inv" Content-Disposition: inline In-Reply-To: <1475479496-16158-19-git-send-email-clg@kaod.org> Subject: Re: [Qemu-devel] [PATCH v4 18/20] ppc/pnv: Add OCC model stub with interrupt support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org --EmW68jKGQIhj8inv Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 03, 2016 at 09:24:54AM +0200, C=E9dric Le Goater wrote: > From: Benjamin Herrenschmidt >=20 > The OCC is an on-chip microcontroller based on a ppc405 core used > for various power management tasks. It comes with a pile of additional > hardware sitting on the PIB (aka XSCOM bus). At this point we don't > emulate it (nor plan to do so). However there is one facility which > is provided by the surrounding hardware that we do need, which is the > interrupt generation facility. OPAL uses it to send itself interrupts > under some circumstances and there are other uses around the corner. >=20 > So this implement just enough to support this. >=20 > Signed-off-by: Benjamin Herrenschmidt > [clg: - updated for qemu-2.7 > - changed the XSCOM interface to fit new model > - QOMified the model ] > Signed-off-by: C=E9dric Le Goater Reviewed-by: David Gibson > --- > hw/ppc/Makefile.objs | 2 +- > hw/ppc/pnv.c | 11 ++++ > hw/ppc/pnv_occ.c | 135 +++++++++++++++++++++++++++++++++++++++= ++++++ > include/hw/ppc/pnv.h | 2 + > include/hw/ppc/pnv_occ.h | 38 +++++++++++++ > include/hw/ppc/pnv_xscom.h | 3 + > 6 files changed, 190 insertions(+), 1 deletion(-) > create mode 100644 hw/ppc/pnv_occ.c > create mode 100644 include/hw/ppc/pnv_occ.h >=20 > diff --git a/hw/ppc/Makefile.objs b/hw/ppc/Makefile.objs > index 4feb15b360c8..35b11cf887d5 100644 > --- a/hw/ppc/Makefile.objs > +++ b/hw/ppc/Makefile.objs > @@ -6,7 +6,7 @@ obj-$(CONFIG_PSERIES) +=3D spapr_hcall.o spapr_iommu.o sp= apr_rtas.o > obj-$(CONFIG_PSERIES) +=3D spapr_pci.o spapr_rtc.o spapr_drc.o spapr_rng= =2Eo > obj-$(CONFIG_PSERIES) +=3D spapr_cpu_core.o > # IBM PowerNV > -obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_ps= i.o > +obj-$(CONFIG_POWERNV) +=3D pnv.o pnv_xscom.o pnv_core.o pnv_lpc.o pnv_ps= i.o pnv_occ.o > ifeq ($(CONFIG_PCI)$(CONFIG_PSERIES)$(CONFIG_LINUX), yyy) > obj-y +=3D spapr_pci_vfio.o > endif > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index b17e205c74db..e805e97d4d87 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -651,6 +651,11 @@ static void pnv_chip_init(Object *obj) > =20 > object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); > object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); > + > + object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); > + object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); > + object_property_add_const_link(OBJECT(&chip->occ), "psi", > + OBJECT(&chip->psi), &error_abort); > } > =20 > static void pnv_chip_realize(DeviceState *dev, Error **errp) > @@ -740,6 +745,12 @@ static void pnv_chip_realize(DeviceState *dev, Error= **errp) > &error_fatal); > memory_region_add_subregion(&chip->xscom, PNV_XSCOM_LPC_BASE << 3, > &chip->lpc.xscom_regs); > + > + /* Create the simplified OCC model */ > + object_property_set_bool(OBJECT(&chip->occ), true, "realized", > + &error_fatal); > + memory_region_add_subregion(&chip->xscom, PNV_XSCOM_OCC_BASE << 3, > + &chip->occ.xscom_regs); > } > =20 > static Property pnv_chip_properties[] =3D { > diff --git a/hw/ppc/pnv_occ.c b/hw/ppc/pnv_occ.c > new file mode 100644 > index 000000000000..250517cca0ef > --- /dev/null > +++ b/hw/ppc/pnv_occ.c > @@ -0,0 +1,135 @@ > +/* > + * QEMU PowerNV Emulation of a few OCC related registers > + * > + * Copyright (c) 2016, IBM Corporation. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License, version 2, as > + * published by the Free Software Foundation. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see . > + */ > + > +#include "qemu/osdep.h" > +#include "hw/hw.h" > +#include "sysemu/sysemu.h" > +#include "target-ppc/cpu.h" > +#include "qapi/error.h" > +#include "qemu/log.h" > + > +#include "hw/ppc/pnv.h" > +#include "hw/ppc/pnv_occ.h" > + > +#define OCB_OCI_OCCMISC 0x4020 > +#define OCB_OCI_OCCMISC_AND 0x4021 > +#define OCB_OCI_OCCMISC_OR 0x4022 > + > +static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) > +{ > + bool irq_state; > + > + val &=3D 0xffff000000000000ull; > + > + occ->occmisc =3D val; > + irq_state =3D !!(val >> 63); > + pnv_psi_irq_set(occ->psi, PSIHB_IRQ_OCC, irq_state); > +} > + > +static uint64_t pnv_occ_xscom_read(void *opaque, hwaddr addr, unsigned s= ize) > +{ > + PnvOCC *occ =3D PNV_OCC(opaque); > + uint32_t offset =3D addr >> 3; > + uint64_t val =3D 0; > + > + switch (offset) { > + case OCB_OCI_OCCMISC: > + val =3D occ->occmisc; > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" > + HWADDR_PRIx "\n", addr); > + } > + return val; > +} > + > +static void pnv_occ_xscom_write(void *opaque, hwaddr addr, > + uint64_t val, unsigned size) > +{ > + PnvOCC *occ =3D PNV_OCC(opaque); > + uint32_t offset =3D addr >> 3; > + > + switch (offset) { > + case OCB_OCI_OCCMISC_AND: > + pnv_occ_set_misc(occ, occ->occmisc & val); > + break; > + case OCB_OCI_OCCMISC_OR: > + pnv_occ_set_misc(occ, occ->occmisc | val); > + break; > + case OCB_OCI_OCCMISC: > + pnv_occ_set_misc(occ, val); > + break; > + default: > + qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" > + HWADDR_PRIx "\n", addr); > + } > +} > + > +static const MemoryRegionOps pnv_occ_xscom_ops =3D { > + .read =3D pnv_occ_xscom_read, > + .write =3D pnv_occ_xscom_write, > + .valid.min_access_size =3D 8, > + .valid.max_access_size =3D 8, > + .impl.min_access_size =3D 8, > + .impl.max_access_size =3D 8, > + .endianness =3D DEVICE_BIG_ENDIAN, > +}; > + > + > +static void pnv_occ_realize(DeviceState *dev, Error **errp) > +{ > + PnvOCC *occ =3D PNV_OCC(dev); > + Object *obj; > + Error *error =3D NULL; > + > + occ->occmisc =3D 0; > + > + /* get PSI object from chip */ > + obj =3D object_property_get_link(OBJECT(dev), "psi", &error); > + if (!obj) { > + error_setg(errp, "%s: required link 'psi' not found: %s", > + __func__, error_get_pretty(error)); > + return; > + } > + occ->psi =3D PNV_PSI(obj); > + > + /* XScom region for OCC registers */ > + memory_region_init_io(&occ->xscom_regs, OBJECT(dev), &pnv_occ_xscom_= ops, > + occ, "xscom-occ", PNV_XSCOM_OCC_SIZE << 3); > +} > + > +static void pnv_occ_class_init(ObjectClass *klass, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(klass); > + > + dc->realize =3D pnv_occ_realize; > +} > + > +static const TypeInfo pnv_occ_type_info =3D { > + .name =3D TYPE_PNV_OCC, > + .parent =3D TYPE_DEVICE, > + .instance_size =3D sizeof(PnvOCC), > + .class_init =3D pnv_occ_class_init, > +}; > + > +static void pnv_occ_register_types(void) > +{ > + type_register_static(&pnv_occ_type_info); > +} > + > +type_init(pnv_occ_register_types) > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > index 473fd2318d87..ed3316501326 100644 > --- a/include/hw/ppc/pnv.h > +++ b/include/hw/ppc/pnv.h > @@ -25,6 +25,7 @@ > #include "hw/ppc/pnv_lpc.h" > #include "hw/ppc/xics.h" > #include "hw/ppc/pnv_psi.h" > +#include "hw/ppc/pnv_occ.h" > =20 > #define TYPE_PNV_CHIP "powernv-chip" > #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) > @@ -59,6 +60,7 @@ typedef struct PnvChip { > PnvLpcController lpc; > XICSNative xics; > PnvPsiController psi; > + PnvOCC occ; > } PnvChip; > =20 > typedef struct PnvChipClass { > diff --git a/include/hw/ppc/pnv_occ.h b/include/hw/ppc/pnv_occ.h > new file mode 100644 > index 000000000000..54e760df7c4f > --- /dev/null > +++ b/include/hw/ppc/pnv_occ.h > @@ -0,0 +1,38 @@ > +/* > + * QEMU PowerNV Emulation of a few OCC related registers > + * > + * Copyright (c) 2016, IBM Corporation. > + * > + * This library is free software; you can redistribute it and/or > + * modify it under the terms of the GNU Lesser General Public > + * License as published by the Free Software Foundation; either > + * version 2 of the License, or (at your option) any later version. > + * > + * This library is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU > + * Lesser General Public License for more details. > + * > + * You should have received a copy of the GNU Lesser General Public > + * License along with this library; if not, see . > + */ > +#ifndef _PPC_PNV_OCC_H > +#define _PPC_PNV_OCC_H > + > +#define TYPE_PNV_OCC "pnv-occ" > +#define PNV_OCC(obj) OBJECT_CHECK(PnvOCC, (obj), TYPE_PNV_OCC) > + > +typedef struct PnvPsiController PnvPsiController; > + > +typedef struct PnvOCC { > + DeviceState xd; > + > + /* OCC Misc interrupt */ > + uint64_t occmisc; > + > + PnvPsiController *psi; > + > + MemoryRegion xscom_regs; > +} PnvOCC; > + > +#endif /* _PPC_PNV_OCC_H */ > diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h > index 28fbec8ee8e0..f22906dc2fff 100644 > --- a/include/hw/ppc/pnv_xscom.h > +++ b/include/hw/ppc/pnv_xscom.h > @@ -66,6 +66,9 @@ typedef struct PnvXScomInterfaceClass { > #define PNV_XSCOM_PSI_BASE 0x2010900 > #define PNV_XSCOM_PSI_SIZE 0x20 > =20 > +#define PNV_XSCOM_OCC_BASE 0x0066000 > +#define PNV_XSCOM_OCC_SIZE 0x6000 > + > extern void pnv_xscom_realize(PnvChip *chip, Error **errp); > extern int pnv_xscom_populate(PnvChip *chip, void *fdt, int offset); > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --EmW68jKGQIhj8inv Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYAHxYAAoJEGw4ysog2bOSGTcP/jfBN/PlwAG+lhO0OXs34b2M dWd5/WVuv3eA0fpi2ADI2enQsCvXE1AT0XfgTa0y9rHXL/DYLVJb6udcfKaVGS09 EcUIJVR9v9qOFCZTSamPIjIQgrZWi+dXVS7e+aHenRoSqX8FbWuguKisAlu8ujzj 3lF2m9czj4lridty4LykBOiAgB2osbSxzR/RTfj0+bt+JjyU/NJDSrh27CCQ1ChX UtsWSNgKVIS46USZDKaueuYevk7cdDN6qubdnbeH9ADLZ9BET1duWmRZ+SOM0IuD 9qJPD/vgpA5C8Hb37qpOubNA7pBynRia7BmrlvNhK7kwst0upJAurmXIF6tsmVw5 tcEXNUPg3KQmM5zMKowfMVINDJGyLSU/hDkTOtl2VtxW+PXTFMt0g4XhFx+wm9py SppSgTxUIkz+YQLIVZifZW78UBlAMgQm5BCXtnoRBWm/5blab8Kx4Db2I+gbiBJ8 AWeQDaov510gFTvAl04ro3BWL9Q4m5y/5A2GrgF6cTiKUVdVdtmkLiAB+4XD42od Uye+7U/KEtYRVqPyeRhD27HjZRwtZuihw086MKhOsxE3TpOJ8xY1LRqZ+AirfEsX zTC8Cbza/l+fr19LNSo94GoUz3TZRCGJkntCpTGlyHgx3xakSQ1PJbYwYSGBkgOj W6K2KlWrdhRBcMCmStfT =wXvB -----END PGP SIGNATURE----- --EmW68jKGQIhj8inv--