From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35575) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bvvnd-0004Rc-U1 for qemu-devel@nongnu.org; Sun, 16 Oct 2016 20:29:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bvvnZ-0006he-Vr for qemu-devel@nongnu.org; Sun, 16 Oct 2016 20:29:05 -0400 Date: Mon, 17 Oct 2016 10:52:06 +1100 From: David Gibson Message-ID: <20161016235206.GG25390@umbus.fritz.box> References: <1475479496-16158-1-git-send-email-clg@kaod.org> <1475479496-16158-18-git-send-email-clg@kaod.org> <20161014063218.GS28562@umbus> <6f1fcee2-2b6c-9033-acb2-98ecbba1fdf8@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="3oCie2+XPXTnK5a5" Content-Disposition: inline In-Reply-To: <6f1fcee2-2b6c-9033-acb2-98ecbba1fdf8@kaod.org> Subject: Re: [Qemu-devel] [PATCH v4 17/20] ppc/pnv: Add cut down PSI bridge model and hookup external interrupt List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org --3oCie2+XPXTnK5a5 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Oct 14, 2016 at 10:07:53AM +0200, C=E9dric Le Goater wrote: > >> --- a/hw/ppc/pnv.c > >> +++ b/hw/ppc/pnv.c > >> @@ -318,15 +318,24 @@ static void ppc_powernv_reset(void) > >> * have a CPLD that will collect the SerIRQ and shoot them as a > >> * single level interrupt to the P8 chip. So let's setup a hook > >> * for doing just that. > >> - * > >> - * Note: The actual interrupt input isn't emulated yet, this will > >> - * come with the PSI bridge model. > >> */ > >> static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int lev= el) > >> { > >> - /* We don't yet emulate the PSI bridge which provides the external > >> - * interrupt, so just drop interrupts on the floor > >> - */ > >> + static uint32_t irqstate; > >=20 > > Hmm.. static local with important state? That it's not clear whether > > it should be per-chip or not? > >=20 > > I'm not averse to hacks for early bringup, but it should at least have > > a FIXME comment on it. >=20 > yes. I will see if I can make a "irq_cpld' attribute of the chip instead.= =20 > It should be cleaner. Wouldn't it be in the machine, not the chip? IIUC there's only one CPLD on the whole board. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --3oCie2+XPXTnK5a5 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYBBKmAAoJEGw4ysog2bOS5/sP/Rm7IJyPqtlv/xXbDDcOjcbT 4u3lMyEfTxu9KDPICKPVxVPxusB0o2X9kKILyM9kTqXSP/uPp+ad5/SgUySDAL74 5oPLrATKgfX8MBgz+gXdgqTzehXrNF+Zk+oxtm06RW/P2Mr2nY+xRD5NpJNqukUe d3VLK/IGzNN66kwcj/BI3dcP6hFKWQfpxjesT+qGMEy5byL/t5eMFyCju8USqHIS u0IBcSedhSnpr78yGyGLuUm4IGsonlEGXG0tPryNSE4RFpdhBI+Eybgrn2ZeoFEW ujOp5Hy/tSx/i/Y4xDV2bCejlStCmDIhgFNLe4l/U0uTcmTuh1F8t7ewb+wXdC08 KK79x0/NeOn6P+sDGH448MhuVO4ACwp1X9zhjeMu99w78MSASl/5MydpWuE//viX 06ELt5mCK4R50SgJDtj63VA7fPzK7HLfEwcchWWu72pvksQZlB+MdjqHG8HDfTpp ciIHdRXmDvalN2dny1ZaNohPIDhqCcIU5/K0nvuDAV9JdSbsjj9Wkb6yS97zlayl cRQh20U67wIC30cCwmY4BIGuGdgTbDD3Bvfp4FtoNQroFyL8huudSeQhNYQnyFJs 6cQAZNXVQWGjsUf5Tnzwzz2ni2ZMEvz7qiHSOC89sexTazIu+usO1ZUGzbD3PYui mdVU/PWjuKnDYcLBjtzb =ufvl -----END PGP SIGNATURE----- --3oCie2+XPXTnK5a5--