From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
To: vijay.kilari@gmail.com
Cc: qemu-arm@nongnu.org, peter.maydell@linaro.org,
pbonzini@redhat.com, rth@twiddle.net, qemu-devel@nongnu.org,
Vijaya Kumar K <Vijaya.Kumar@cavium.com>
Subject: Re: [Qemu-devel] [PATCH v3 2/3] utils: Add helper to read arm MIDR_EL1 register
Date: Mon, 24 Oct 2016 10:39:44 +0100 [thread overview]
Message-ID: <20161024093943.GC2190@work-vm> (raw)
In-Reply-To: <1477288523-10819-3-git-send-email-vijay.kilari@gmail.com>
* vijay.kilari@gmail.com (vijay.kilari@gmail.com) wrote:
> From: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
>
> Add helper API to read MIDR_EL1 registers to fetch
> cpu identification information. This helps in
> adding errata's and architecture specific features.
>
> This is implemented only for arm architecture.
>
> Signed-off-by: Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> ---
> include/qemu/aarch64-cpuid.h | 9 +++++
> util/Makefile.objs | 1 +
> util/aarch64-cpuid.c | 87 ++++++++++++++++++++++++++++++++++++++++++++
It feels like there should be somewhere else to put this very ARM specific thing
that in util/ - not sure where though.
> 3 files changed, 97 insertions(+)
>
> diff --git a/include/qemu/aarch64-cpuid.h b/include/qemu/aarch64-cpuid.h
> new file mode 100644
> index 0000000..dbcb5ff
> --- /dev/null
> +++ b/include/qemu/aarch64-cpuid.h
> @@ -0,0 +1,9 @@
> +#ifndef QEMU_AARCH64_CPUID_H
> +#define QEMU_AARCH64_CPUID_H
> +
> +#if defined(__aarch64__)
> +uint64_t get_aarch64_cpu_id(void);
> +bool is_thunderx_pass2_cpu(void);
> +#endif
> +
> +#endif
> diff --git a/util/Makefile.objs b/util/Makefile.objs
> index 36c7dcc..d14a455 100644
> --- a/util/Makefile.objs
> +++ b/util/Makefile.objs
> @@ -37,3 +37,4 @@ util-obj-y += log.o
> util-obj-y += qdist.o
> util-obj-y += qht.o
> util-obj-y += range.o
> +util-obj-y += aarch64-cpuid.o
> diff --git a/util/aarch64-cpuid.c b/util/aarch64-cpuid.c
> new file mode 100644
> index 0000000..a6352ad
> --- /dev/null
> +++ b/util/aarch64-cpuid.c
> @@ -0,0 +1,87 @@
> +/*
> + * Dealing with arm cpu identification information.
> + *
> + * Copyright (C) 2016 Cavium, Inc.
> + *
> + * Authors:
> + * Vijaya Kumar K <Vijaya.Kumar@cavium.com>
> + *
> + * This work is licensed under the terms of the GNU LGPL, version 2.1
> + * or later. See the COPYING.LIB file in the top-level directory.
> + */
> +
> +#include <math.h>
> +#include "qemu/osdep.h"
> +#include "qemu-common.h"
> +#include "qemu/cutils.h"
> +#include "qemu/aarch64-cpuid.h"
> +
> +#if defined(__aarch64__)
> +#define MIDR_IMPLEMENTER_SHIFT 24
> +#define MIDR_IMPLEMENTER_MASK (0xffULL << MIDR_IMPLEMENTER_SHIFT)
> +#define MIDR_ARCHITECTURE_SHIFT 16
> +#define MIDR_ARCHITECTURE_MASK (0xf << MIDR_ARCHITECTURE_SHIFT)
> +#define MIDR_PARTNUM_SHIFT 4
> +#define MIDR_PARTNUM_MASK (0xfff << MIDR_PARTNUM_SHIFT)
> +
> +#define MIDR_CPU_PART(imp, partnum) \
> + (((imp) << MIDR_IMPLEMENTER_SHIFT) | \
> + (0xf << MIDR_ARCHITECTURE_SHIFT) | \
> + ((partnum) << MIDR_PARTNUM_SHIFT))
> +
> +#define ARM_CPU_IMP_CAVIUM 0x43
> +#define CAVIUM_CPU_PART_THUNDERX 0x0A1
> +
> +#define MIDR_THUNDERX_PASS2 \
> + MIDR_CPU_PART(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
> +#define CPU_MODEL_MASK (MIDR_IMPLEMENTER_MASK | MIDR_ARCHITECTURE_MASK | \
> + MIDR_PARTNUM_MASK)
> +
> +static uint64_t qemu_read_aarch64_midr_el1(void)
> +{
> +#ifdef CONFIG_LINUX
> + const char *file = "/sys/devices/system/cpu/cpu0/regs/identification/midr_el1";
> + char *buf;
> + uint64_t midr = 0;
> +
> +#define BUF_SIZE 32
> + buf = g_malloc0(BUF_SIZE);
> + if (!buf) {
> + return 0;
> + }
Do you need to do that? Isn't g_file_get_contents doing the allocation?
Dave
> + if (!g_file_get_contents(file, &buf, 0, NULL)) {
> + goto out;
> + }
> +
> + if (qemu_strtoull(buf, NULL, 0, &midr) < 0) {
> + goto out;
> + }
> +
> +out:
> + g_free(buf);
> +
> + return midr;
> +#else
> + return 0;
> +#endif
> +}
> +
> +static uint64_t aarch64_midr_val;
> +uint64_t get_aarch64_cpu_id(void)
> +{
> +#ifdef CONFIG_LINUX
> + aarch64_midr_val = qemu_read_aarch64_midr_el1();
> + aarch64_midr_val &= CPU_MODEL_MASK;
> +
> + return aarch64_midr_val;
> +#else
> + return 0;
> +#endif
> +}
> +
> +bool is_thunderx_pass2_cpu(void)
> +{
> + return aarch64_midr_val == MIDR_THUNDERX_PASS2;
> +}
> +#endif
> --
> 1.9.1
>
>
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
next prev parent reply other threads:[~2016-10-24 9:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-24 5:55 [Qemu-devel] [PATCH v3 0/3] Live migration optimization for Thunderx platform vijay.kilari
2016-10-24 5:55 ` [Qemu-devel] [PATCH v3 1/3] cutils: Set __builtin_prefetch optional parameters vijay.kilari
2016-10-24 15:43 ` Richard Henderson
2016-10-24 5:55 ` [Qemu-devel] [PATCH v3 2/3] utils: Add helper to read arm MIDR_EL1 register vijay.kilari
2016-10-24 9:39 ` Dr. David Alan Gilbert [this message]
2016-10-24 10:20 ` Vijay Kilari
2016-10-24 11:26 ` Paolo Bonzini
2016-10-24 15:47 ` Richard Henderson
2016-10-24 5:55 ` [Qemu-devel] [PATCH v3 3/3] utils: Add prefetch for Thunderx platform vijay.kilari
2016-10-24 11:25 ` Paolo Bonzini
2016-10-24 15:51 ` Richard Henderson
2016-10-24 15:47 ` [Qemu-devel] [PATCH v3 0/3] Live migration optimization " Richard Henderson
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