From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46671) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1byuPl-0007Sw-Cy for qemu-devel@nongnu.org; Tue, 25 Oct 2016 01:36:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1byuPi-00087i-8e for qemu-devel@nongnu.org; Tue, 25 Oct 2016 01:36:45 -0400 Date: Tue, 25 Oct 2016 16:11:10 +1100 From: David Gibson Message-ID: <20161025051110.GY11052@umbus.fritz.box> References: <1477129610-31353-1-git-send-email-clg@kaod.org> <1477129610-31353-13-git-send-email-clg@kaod.org> <8762d423-e6a9-97c0-35a3-59e9f7f12089@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="AAkN98o3X3ouhQaz" Content-Disposition: inline In-Reply-To: <8762d423-e6a9-97c0-35a3-59e9f7f12089@kaod.org> Subject: Re: [Qemu-devel] [PATCH v5 12/17] ppc/pnv: add a XICS native to each PowerNV chip List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, Benjamin Herrenschmidt , qemu-devel@nongnu.org, Alexander Graf --AAkN98o3X3ouhQaz Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Oct 24, 2016 at 05:42:52PM +0200, C=E9dric Le Goater wrote: > On 10/22/2016 11:46 AM, C=E9dric Le Goater wrote: > > It also links the XICS object to each core as it is needed to do the > > CPU setup and the ICP MMIO windows are memory mapped for each thread. > >=20 > > Signed-off-by: C=E9dric Le Goater > > --- > >=20 > > Changes since v4: > >=20 > > - changed the calculation of the number of ICPs to use smp_threads > > - added the mapping of the ICP subregions per thread > >=20 > > hw/ppc/pnv.c | 27 +++++++++++++++++++++++++++ > > hw/ppc/pnv_core.c | 24 ++++++++++++++++++++---- > > include/hw/ppc/pnv.h | 2 ++ > > 3 files changed, 49 insertions(+), 4 deletions(-) > >=20 > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > > index c6dc7ca895b6..16d7baf0da71 100644 > > --- a/hw/ppc/pnv.c > > +++ b/hw/ppc/pnv.c > > @@ -33,6 +33,7 @@ > > #include "qemu/cutils.h" > > #include "qapi/visitor.h" > > =20 > > +#include "hw/ppc/xics.h" > > #include "hw/ppc/pnv_xscom.h" > > =20 > > #include "hw/isa/isa.h" > > @@ -231,6 +232,9 @@ static void powernv_populate_chip(PnvChip *chip, vo= id *fdt) > > PnvCore *pnv_core =3D PNV_CORE(chip->cores + i * typesize); > > =20 > > powernv_create_core_node(chip, pnv_core, fdt); > > + > > + /* Interrupt presentation controllers (ICP). One per thread. */ > > + xics_native_populate_icp(chip, fdt, 0, pnv_core->pir, smp_thre= ads); > > } > > =20 > > if (chip->ram_size) { > > @@ -637,6 +641,9 @@ static void pnv_chip_init(Object *obj) > > =20 > > object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); > > object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); > > + > > + object_initialize(&chip->xics, sizeof(chip->xics), TYPE_XICS_NATIV= E); > > + object_property_add_child(obj, "xics", OBJECT(&chip->xics), NULL); > > } > > =20 > > static void pnv_chip_realize(DeviceState *dev, Error **errp) > > @@ -668,12 +675,23 @@ static void pnv_chip_realize(DeviceState *dev, Er= ror **errp) > > return; > > } > > =20 > > + /* > > + * Interrupt Controller. To be created before the cores because > > + * each thread will fetch its ICP in the XICS > > + */ > > + object_property_set_int(OBJECT(&chip->xics), chip->nr_cores * smp_= threads, > > + "nr_servers", &error_fatal); > > + object_property_set_bool(OBJECT(&chip->xics), true, "realized", > > + &error_fatal); > > + sysbus_mmio_map(SYS_BUS_DEVICE(&chip->xics), 0, PNV_XICS_BASE); > > + > > chip->cores =3D g_malloc0(typesize * chip->nr_cores); > > =20 > > for (i =3D 0, core_hwid =3D 0; (core_hwid < sizeof(chip->cores_mas= k) * 8) > > && (i < chip->nr_cores); core_hwid++) { > > char core_name[32]; > > void *pnv_core =3D chip->cores + i * typesize; > > + int j; > > =20 > > if (!(chip->cores_mask & (1ull << core_hwid))) { > > continue; > > @@ -690,6 +708,8 @@ static void pnv_chip_realize(DeviceState *dev, Erro= r **errp) > > object_property_set_int(OBJECT(pnv_core), > > pcc->core_pir(chip, core_hwid), > > "pir", &error_fatal); > > + object_property_add_const_link(OBJECT(pnv_core), "xics", > > + OBJECT(&chip->xics), &error_fat= al); > > object_property_set_bool(OBJECT(pnv_core), true, "realized", > > &error_fatal); > > object_unref(OBJECT(pnv_core)); > > @@ -697,6 +717,13 @@ static void pnv_chip_realize(DeviceState *dev, Err= or **errp) > > /* Each core has an XSCOM MMIO region */ > > pnv_xscom_add_subregion(chip, PNV_XSCOM_EX_CORE_BASE(core_hwid= ), > > &PNV_CORE(pnv_core)->xscom_regs); > > + > > + /* Each thread as region for its ICP */ > > + for (j =3D 0; j < smp_threads; j++) { > > + memory_region_add_subregion(&chip->xics.icp_mmio, > > + pcc->core_pir(chip, core_hwid)= << 12, >=20 > Pffut ... This should be : >=20 > (pcc->core_pir(chip, core_hwid)= + j) << 12, >=20 > but as smp_threads=3D1, it has no consequences for the moment. Tell me=20 > how you would prefer me to fix this. I think I have enough comments on the previous patch that a respin of patches 11+ will make sense, so just fix it then. >=20 > Thanks, >=20 > C. >=20 >=20 > > + &chip->xics.icp_mmios[i]); > > + } > > i++; > > } > > g_free(typename); > > diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c > > index 2acda9637db5..e15c76163759 100644 > > --- a/hw/ppc/pnv_core.c > > +++ b/hw/ppc/pnv_core.c > > @@ -24,6 +24,7 @@ > > #include "hw/ppc/ppc.h" > > #include "hw/ppc/pnv.h" > > #include "hw/ppc/pnv_core.h" > > +#include "hw/ppc/xics.h" > > =20 > > static void powernv_cpu_reset(void *opaque) > > { > > @@ -42,7 +43,7 @@ static void powernv_cpu_reset(void *opaque) > > env->msr |=3D MSR_HVB; /* Hypervisor mode */ > > } > > =20 > > -static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp) > > +static void powernv_cpu_init(PowerPCCPU *cpu, XICSState *xics, Error *= *errp) > > { > > CPUPPCState *env =3D &cpu->env; > > int core_pir; > > @@ -62,6 +63,11 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error = **errp) > > cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); > > =20 > > qemu_register_reset(powernv_cpu_reset, cpu); > > + > > + /* > > + * xics_cpu_setup() assigns the CPU to the ICP in XICS > > + */ > > + xics_cpu_setup(xics, cpu); > > } > > =20 > > /* > > @@ -109,7 +115,7 @@ static const MemoryRegionOps pnv_core_xscom_ops =3D= { > > .endianness =3D DEVICE_BIG_ENDIAN, > > }; > > =20 > > -static void pnv_core_realize_child(Object *child, Error **errp) > > +static void pnv_core_realize_child(Object *child, XICSState *xics, Err= or **errp) > > { > > Error *local_err =3D NULL; > > CPUState *cs =3D CPU(child); > > @@ -121,7 +127,7 @@ static void pnv_core_realize_child(Object *child, E= rror **errp) > > return; > > } > > =20 > > - powernv_cpu_init(cpu, &local_err); > > + powernv_cpu_init(cpu, xics, &local_err); > > if (local_err) { > > error_propagate(errp, local_err); > > return; > > @@ -139,6 +145,7 @@ static void pnv_core_realize(DeviceState *dev, Erro= r **errp) > > void *obj; > > int i, j; > > char name[32]; > > + XICSState *xics; > > =20 > > pc->threads =3D g_malloc0(size * cc->nr_threads); > > for (i =3D 0; i < cc->nr_threads; i++) { > > @@ -156,10 +163,19 @@ static void pnv_core_realize(DeviceState *dev, Er= ror **errp) > > object_unref(obj); > > } > > =20 > > + /* get XICS object from chip */ > > + obj =3D object_property_get_link(OBJECT(dev), "xics", &local_err); > > + if (!obj) { > > + error_setg(errp, "%s: required link 'xics' not found: %s", > > + __func__, error_get_pretty(local_err)); > > + return; > > + } > > + xics =3D XICS_COMMON(obj); > > + > > for (j =3D 0; j < cc->nr_threads; j++) { > > obj =3D pc->threads + j * size; > > =20 > > - pnv_core_realize_child(obj, &local_err); > > + pnv_core_realize_child(obj, xics, &local_err); > > if (local_err) { > > goto err; > > } > > diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h > > index c08ed1c72b17..e11618b05f1d 100644 > > --- a/include/hw/ppc/pnv.h > > +++ b/include/hw/ppc/pnv.h > > @@ -23,6 +23,7 @@ > > #include "hw/sysbus.h" > > #include "hw/ppc/pnv_xscom.h" > > #include "hw/ppc/pnv_lpc.h" > > +#include "hw/ppc/xics.h" > > =20 > > #define TYPE_PNV_CHIP "powernv-chip" > > #define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP) > > @@ -57,6 +58,7 @@ typedef struct PnvChip { > > AddressSpace xscom_as; > > =20 > > PnvLpcController lpc; > > + XICSNative xics; > > } PnvChip; > > =20 > > typedef struct PnvChipClass { > >=20 >=20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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