From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40577) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bz0fE-0007eZ-Gj for qemu-devel@nongnu.org; Tue, 25 Oct 2016 08:17:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bz0fA-0003pu-H9 for qemu-devel@nongnu.org; Tue, 25 Oct 2016 08:17:08 -0400 Date: Tue, 25 Oct 2016 23:16:54 +1100 From: David Gibson Message-ID: <20161025121654.GD11052@umbus.fritz.box> References: <1477285201-10244-1-git-send-email-david@gibson.dropbear.id.au> <1477285201-10244-8-git-send-email-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="jcjv6D8puUawUjle" Content-Disposition: inline In-Reply-To: Subject: Re: [Qemu-devel] [PATCHv5 07/12] libqos: Implement mmio accessors in terms of mem{read, write} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexey Kardashevskiy Cc: pbonzini@redhat.com, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, lvivier@redhat.com, agraf@suse.de, stefanha@redhat.com, mst@redhat.com, mdroth@linux.vnet.ibm.com, groug@kaod.org, thuth@redhat.com --jcjv6D8puUawUjle Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Oct 25, 2016 at 05:47:43PM +1100, Alexey Kardashevskiy wrote: > On 24/10/16 15:59, David Gibson wrote: > > In the libqos PCI code we now have accessors both for registers (byte > > significance preserving) and for streaming data (byte address order > > preserving). These exist in both the interface for qtest drivers and in > > the machine specific backends. > >=20 > > However, the register-style accessors aren't actually necessary in the > > backend. They can be implemented in terms of the byte address order > > preserving accessors by the libqos wrappers. This works because PCI is > > always little endian. > >=20 > > This does assume that the back end byte address order preserving access= ors > > will perform the equivalent of a single bus transaction for short lengt= hs. > > This is the case, and in fact they currently end up using the same > > cpu_physical_memory_rw() implementation within the qtest accelerator. > >=20 > > Signed-off-by: David Gibson > > Reviewed-by: Laurent Vivier > > Reviewed-by: Greg Kurz > > --- > > tests/libqos/pci-pc.c | 38 -------------------------------------- > > tests/libqos/pci-spapr.c | 44 ----------------------------------------= ---- > > tests/libqos/pci.c | 20 ++++++++++++++------ > > tests/libqos/pci.h | 8 -------- > > 4 files changed, 14 insertions(+), 96 deletions(-) > >=20 >=20 > [...] >=20 > > diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h > > index 2b08362..ce6ed08 100644 > > --- a/tests/libqos/pci.h > > +++ b/tests/libqos/pci.h > > @@ -27,18 +27,10 @@ struct QPCIBus { > > uint16_t (*pio_readw)(QPCIBus *bus, uint32_t addr); > > uint32_t (*pio_readl)(QPCIBus *bus, uint32_t addr); > > =20 > > - uint8_t (*mmio_readb)(QPCIBus *bus, uint32_t addr); > > - uint16_t (*mmio_readw)(QPCIBus *bus, uint32_t addr); > > - uint32_t (*mmio_readl)(QPCIBus *bus, uint32_t addr); > > - > > void (*pio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value); > > void (*pio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value); > > void (*pio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value); > > =20 > > - void (*mmio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value); > > - void (*mmio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value); > > - void (*mmio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value); > > - > > void (*memread)(QPCIBus *bus, uint32_t addr, void *buf, size_t len= ); > > void (*memwrite)(QPCIBus *bus, uint32_t addr, const void *buf, siz= e_t len); > > =20 > >=20 >=20 > You added them in "libqos: Handle PCI IO de-multiplexing in common code" > (few patched before) and removing them now - if you moved this patch > earlier, it would reduce the series, or what do I miss? Well, it can't go before the PIO / MMIO split, because on x86 the PIO part is implemented with inw/outw instead of readw/writew, and those don't have a memread/memwrite equivalent. The change could go at the same time, but my feeling was that logical separation of the steps was worth a bit of temporary extra code. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --jcjv6D8puUawUjle Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJYD00zAAoJEGw4ysog2bOSCzMP/3769CW6cZ2WgP7rEl+x35Mi N2HC5Bc5x2bkJ8bU9537qC4YeqkI0Pm20p8EoLB1jyMG4EWXVpLur+7t1y90wt0b NDcSPYyErZvPEHnmqDqFdW/6n7P5QKKObUY1tdNYOk+ZJY2ViKKWbssNu6ROffGQ dYh7TD9Veq9UHBKuudRQAIPcFXFkI2zhHmjN+AVdVzETKv5IFkys/P2jjHSRvngK gri/Dfr+RW1I+Ptnx+kSd7+6+JmZWStB4yj7SAr/tep19e8WjO1i0a77zCNo0e3t gnOOh3ChuUBSHfr4iqzi+Mfd3devTCFM6euZLAwuHseDvtIUeIlTPNZ95X5LW6hv fbgQ1NqmSfCIRvP5PVfyTa5niczLXycB7/C9m/Ov0WOumHJh7sLdtHqUNHwenhvt V21kOtE4uJDNryEVMbV765XmQ9n2OtHS8GtU13ONbRnT9Nwrg051/7j5iQbQxVbg zOa9+BhJklLm6t8+QuN/y0ujjO6T/uAu8gayuemc2PHcVypiD7x1CjBch5WqWvA3 RuzitvI9oZs2koU32Evr7xDffsv/9OpRXD2cLRZqVXXFsIRNCe1EuWQ7trd3dLMk UUXt2Sa2FbE7lBUr+nUxF5I7vCpgqY7UfS3+sD70ldvaQtIYXEFwBZwtsgwzJO14 1MI/w7mb2VS2D1cxaw8C =blBj -----END PGP SIGNATURE----- --jcjv6D8puUawUjle--