From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38853) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c19w7-0004bb-6j for qemu-devel@nongnu.org; Mon, 31 Oct 2016 06:35:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c19w4-0001RA-0W for qemu-devel@nongnu.org; Mon, 31 Oct 2016 06:35:27 -0400 Received: from 20.mo5.mail-out.ovh.net ([91.121.55.239]:60767) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c19w3-0001Qq-Qi for qemu-devel@nongnu.org; Mon, 31 Oct 2016 06:35:23 -0400 Received: from player774.ha.ovh.net (b7.ovh.net [213.186.33.57]) by mo5.mail-out.ovh.net (Postfix) with ESMTP id 2E4A240EDD for ; Mon, 31 Oct 2016 11:35:22 +0100 (CET) Date: Mon, 31 Oct 2016 11:35:11 +0100 From: Greg Kurz Message-ID: <20161031113511.414cb6d5@bahia> In-Reply-To: <1477825928-10803-3-git-send-email-david@gibson.dropbear.id.au> References: <1477825928-10803-1-git-send-email-david@gibson.dropbear.id.au> <1477825928-10803-3-git-send-email-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC 02/17] powernv: CPU compatibility modes don't make sense for powernv List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: nikunj@linux.vnet.ibm.com, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com, lvivier@redhat.com, thuth@redhat.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org On Sun, 30 Oct 2016 22:11:53 +1100 David Gibson wrote: > powernv has some code (derived from the spapr equivalent) used in device > tree generation which depends on the CPU's compatibility mode / logical > PVR. However, compatibility modes don't make sense on powernv - at least > not as a property controlled by the host - because the guest in powernv > has full hypervisor level access to the virtual system, and so owns the > PCR (Processor Compatibility Register) which implements compatiblity modes. > > Signed-off-by: David Gibson > --- As said with the standalone version: Reviewed-by: Greg Kurz > hw/ppc/pnv.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 82276e0..6af3424 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -110,7 +110,7 @@ static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) > CPUState *cs = CPU(DEVICE(pc->threads)); > DeviceClass *dc = DEVICE_GET_CLASS(cs); > PowerPCCPU *cpu = POWERPC_CPU(cs); > - int smt_threads = ppc_get_compat_smt_threads(cpu); > + int smt_threads = CPU_CORE(pc)->nr_threads; > CPUPPCState *env = &cpu->env; > PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); > uint32_t servers_prop[smt_threads]; > @@ -206,10 +206,6 @@ static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) > _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", > pa_features, sizeof(pa_features)))); > > - if (cpu->cpu_version) { > - _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", cpu->cpu_version))); > - } > - > /* Build interrupt servers properties */ > for (i = 0; i < smt_threads; i++) { > servers_prop[i] = cpu_to_be32(pc->pir + i);