From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48902) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c5Cgv-0000VH-A3 for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c5Cgs-0007hW-96 for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:29 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:36872) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c5Cgs-0007gK-2e for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:26 -0500 From: Bastian Koppelmann Date: Fri, 11 Nov 2016 15:20:14 +0100 Message-Id: <20161111142018.22567-2-kbastian@mail.uni-paderborn.de> In-Reply-To: <20161111142018.22567-1-kbastian@mail.uni-paderborn.de> References: <20161111142018.22567-1-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v3 1/5] target-tricore: Added FTOUZ instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net Converts a 32-bit floating point number to an unsigned int. The result is rounded towards zero. Signed-off-by: Bastian Koppelmann --- v2 -> v3: - simplified exception flag fixup in ftouz() target-tricore/fpu_helper.c | 27 +++++++++++++++++++++++++++ target-tricore/helper.h | 1 + target-tricore/translate.c | 3 +++ 3 files changed, 31 insertions(+) diff --git a/target-tricore/fpu_helper.c b/target-tricore/fpu_helper.c index 98fe947..215c397 100644 --- a/target-tricore/fpu_helper.c +++ b/target-tricore/fpu_helper.c @@ -215,3 +215,30 @@ uint32_t helper_itof(CPUTriCoreState *env, uint32_t arg) } return (uint32_t)f_result; } + +uint32_t helper_ftouz(CPUTriCoreState *env, uint32_t arg) +{ + float32 f_arg = make_float32(arg); + uint32_t result; + int32_t flags; + + result = float32_to_uint32_round_to_zero(f_arg, &env->fp_status); + + flags = f_get_excp_flags(env); + if (flags & float_flag_invalid) { + flags &= ~float_flag_inexact; + if (float32_is_any_nan(f_arg)) { + result = 0; + } + } else if (float32_lt_quiet(f_arg, 0, &env->fp_status)) { + flags = float_flag_invalid; + result = 0; + } + + if (flags) { + f_update_psw_flags(env, flags); + } else { + env->FPU_FS = 0; + } + return result; +} diff --git a/target-tricore/helper.h b/target-tricore/helper.h index 9333e16..467c880 100644 --- a/target-tricore/helper.h +++ b/target-tricore/helper.h @@ -112,6 +112,7 @@ DEF_HELPER_3(fdiv, i32, env, i32, i32) DEF_HELPER_3(fcmp, i32, env, i32, i32) DEF_HELPER_2(ftoi, i32, env, i32) DEF_HELPER_2(itof, i32, env, i32) +DEF_HELPER_2(ftouz, i32, env, i32) /* dvinit */ DEF_HELPER_3(dvinit_b_13, i64, env, i32, i32) DEF_HELPER_3(dvinit_b_131, i64, env, i32, i32) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 36f734a..eb6fdc3 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6698,6 +6698,9 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_ITOF: gen_helper_itof(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); break; + case OPC2_32_RR_FTOUZ: + gen_helper_ftouz(cpu_gpr_d[r3], cpu_env, cpu_gpr_d[r1]); + break; default: generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); } -- 2.10.2