From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48912) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c5Cgv-0000VP-Dm for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c5Cgs-0007hQ-7M for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:29 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:42829) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c5Cgs-0007gW-0C for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:26 -0500 From: Bastian Koppelmann Date: Fri, 11 Nov 2016 15:20:16 +0100 Message-Id: <20161111142018.22567-4-kbastian@mail.uni-paderborn.de> In-Reply-To: <20161111142018.22567-1-kbastian@mail.uni-paderborn.de> References: <20161111142018.22567-1-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v3 3/5] target-tricore: Added new MOV instruction variant List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net, Peer Adelt From: Peer Adelt Puts the content of data register D[a] into E[c][63:32] and the content of data register D[b] into E[c][31:0]. [BK: fix style error] [BK: Allocate temporaries only when needed] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-4-git-send-email-peer.adelt@c-lab.de> --- v2 -> v3: - Allocate temporaries only when needed target-tricore/translate.c | 16 ++++++++++++++++ target-tricore/tricore-opcodes.h | 1 + 2 files changed, 17 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index a8234db..1cdd87e 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -6034,6 +6034,8 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) uint32_t op2; int r3, r2, r1; + TCGv temp; + r3 = MASK_OP_RR_D(ctx->opcode); r2 = MASK_OP_RR_S2(ctx->opcode); r1 = MASK_OP_RR_S1(ctx->opcode); @@ -6224,6 +6226,20 @@ static void decode_rr_accumulator(CPUTriCoreState *env, DisasContext *ctx) case OPC2_32_RR_MOV: tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); break; + case OPC2_32_RR_MOV_64: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + temp = tcg_temp_new(); + + CHECK_REG_PAIR(r3); + tcg_gen_mov_tl(temp, cpu_gpr_d[r1]); + tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r2]); + tcg_gen_mov_tl(cpu_gpr_d[r3 + 1], temp); + + tcg_temp_free(temp); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; case OPC2_32_RR_NE: tcg_gen_setcond_tl(TCG_COND_NE, cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2]); diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index df666b0..78ba338 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -1062,6 +1062,7 @@ enum { OPC2_32_RR_MIN_H = 0x78, OPC2_32_RR_MIN_HU = 0x79, OPC2_32_RR_MOV = 0x1f, + OPC2_32_RR_MOV_64 = 0x81, OPC2_32_RR_NE = 0x11, OPC2_32_RR_OR_EQ = 0x27, OPC2_32_RR_OR_GE = 0x2b, -- 2.10.2