From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48907) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c5Cgv-0000VM-BF for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c5Cgs-0007hA-5S for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:29 -0500 Received: from mail.uni-paderborn.de ([131.234.142.9]:42827) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1c5Cgr-0007gV-UI for qemu-devel@nongnu.org; Fri, 11 Nov 2016 09:20:26 -0500 From: Bastian Koppelmann Date: Fri, 11 Nov 2016 15:20:17 +0100 Message-Id: <20161111142018.22567-5-kbastian@mail.uni-paderborn.de> In-Reply-To: <20161111142018.22567-1-kbastian@mail.uni-paderborn.de> References: <20161111142018.22567-1-kbastian@mail.uni-paderborn.de> Subject: [Qemu-devel] [PATCH v3 4/5] target-tricore: Added new JNE instruction variant List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: rth@twiddle.net, Peer Adelt From: Peer Adelt If D[15] is != sign_ext(const4) then PC will be set to (PC + zero_ext(disp4 + 16)). [BK: fixed style errors] Signed-off-by: Peer Adelt Message-Id: <1465314555-11501-5-git-send-email-peer.adelt@c-lab.de> --- target-tricore/translate.c | 18 ++++++++++++++++++ target-tricore/tricore-opcodes.h | 2 ++ 2 files changed, 20 insertions(+) diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 1cdd87e..9d1ee66 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3362,9 +3362,17 @@ static void gen_compute_branch(DisasContext *ctx, uint32_t opc, int r1, case OPC1_16_SBC_JEQ: gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, offset); break; + case OPC1_16_SBC_JEQ2: + gen_branch_condi(ctx, TCG_COND_EQ, cpu_gpr_d[15], constant, + offset + 16); + break; case OPC1_16_SBC_JNE: gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], constant, offset); break; + case OPC1_16_SBC_JNE2: + gen_branch_condi(ctx, TCG_COND_NE, cpu_gpr_d[15], + constant, offset + 16); + break; /* SBRN-format jumps */ case OPC1_16_SBRN_JZ_T: temp = tcg_temp_new(); @@ -4097,6 +4105,16 @@ static void decode_16Bit_opc(CPUTriCoreState *env, DisasContext *ctx) const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); gen_compute_branch(ctx, op1, 0, 0, const16, address); break; + case OPC1_16_SBC_JEQ2: + case OPC1_16_SBC_JNE2: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + address = MASK_OP_SBC_DISP4(ctx->opcode); + const16 = MASK_OP_SBC_CONST4_SEXT(ctx->opcode); + gen_compute_branch(ctx, op1, 0, 0, const16, address); + } else { + generate_trap(ctx, TRAPC_INSN_ERR, TIN2_IOPC); + } + break; /* SBRN-format */ case OPC1_16_SBRN_JNZ_T: case OPC1_16_SBRN_JZ_T: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 78ba338..08394b8 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -311,6 +311,7 @@ enum { OPC1_16_SRR_EQ = 0x3a, OPC1_16_SB_J = 0x3c, OPC1_16_SBC_JEQ = 0x1e, + OPC1_16_SBC_JEQ2 = 0x9e, OPC1_16_SBR_JEQ = 0x3e, OPC1_16_SBR_JGEZ = 0xce, OPC1_16_SBR_JGTZ = 0x4e, @@ -318,6 +319,7 @@ enum { OPC1_16_SBR_JLEZ = 0x8e, OPC1_16_SBR_JLTZ = 0x0e, OPC1_16_SBC_JNE = 0x5e, + OPC1_16_SBC_JNE2 = 0xde, OPC1_16_SBR_JNE = 0x7e, OPC1_16_SB_JNZ = 0xee, OPC1_16_SBR_JNZ = 0xf6, -- 2.10.2