From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57528) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c6Yfv-0008Ug-9y for qemu-devel@nongnu.org; Tue, 15 Nov 2016 03:01:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c6Yfr-0008GP-UK for qemu-devel@nongnu.org; Tue, 15 Nov 2016 03:01:03 -0500 Received: from indium.canonical.com ([91.189.90.7]:33195) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c6Yfr-0008Fr-On for qemu-devel@nongnu.org; Tue, 15 Nov 2016 03:00:59 -0500 Received: from loganberry.canonical.com ([91.189.90.37]) by indium.canonical.com with esmtp (Exim 4.76 #1 (Debian)) id 1c6Yfp-0004ON-Ba for ; Tue, 15 Nov 2016 08:00:57 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id 3FF8C2E80C6 for ; Tue, 15 Nov 2016 08:00:57 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Tue, 15 Nov 2016 07:51:12 -0000 From: Jie <1641861@bugs.launchpad.net> Reply-To: Bug 1641861 <1641861@bugs.launchpad.net> Sender: bounces@canonical.com Message-Id: <20161115075112.3631.29997.malonedeb@soybean.canonical.com> Errors-To: bounces@canonical.com Subject: [Qemu-devel] [Bug 1641861] [NEW] fail to correctly emulate FPSCR register on arm List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Public bug reported: Hi all, we systematically tested the QEMU implementation for emulating arm user mode programs. We found that QEMU incorrectly emulate the FPSCR register. The following the proof of code: /*********** Beginning of the bug: arm.c **********/ int printf(const char *format, ...); unsigned char i0[0x10]; unsigned char o[0x10]; int main() { =C2=A0=C2=A0=C2=A0=C2=A0int k =3D 0; =C2=A0=C2=A0=C2=A0=C2=A0asm("mov r2, %0\n" =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"ldr r0, [r2]\n"::"r"((char= *)(i0)));; =C2=A0=C2=A0=C2=A0=C2=A0asm("vmsr fpscr, r0"); =C2=A0=C2=A0=C2=A0=C2=A0asm("mov r2, %0\n" =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"vmrs r4, fpscr\n" =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"str r4, [r2]\n"::"r"((char= *)(o)));; =C2=A0=C2=A0=C2=A0=C2=A0for (k =3D 0; k < 0x10; k++) =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0printf("%02x", o[0x10 - 1 -= k]); =C2=A0=C2=A0=C2=A0=C2=A0printf("\n"); } unsigned char i0[0x10] =3D {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,= 0x28, 0x1c, 0xc7, 0x01, 0x00, 0x00, 0x00, 0x00}; /*********** End fo the bug **********/ When the program is compiled into arm binary code and running on a real arm machine, and running in qemu, we have the following result $ arm-linux-gnueabihf-gcc arm.c -o arm -static $ ./arm 000000000000000000000000fff7009f $ qemu-arm arm 000000000000000000000000ffffffff According to the ARM manual, bits[19, 14:13, 6:5] of FPSCR should be reserved as zero. However, arm qemu fails to keep these bits to be zero: these bits can be actually modified in QEMU. QEMU version is 2.7.0. The operating system is Linux 3.13.0. x86_64. Thanks! ** Affects: qemu Importance: Undecided Status: New ** Description changed: Hi all, we systematically tested the QEMU implementation for emulating arm user mode programs. We found that QEMU incorrectly emulate the FPSCR register. The following the proof of code: = /*********** Beginning of the bug: arm.c **********/ = int printf(const char *format, ...); unsigned char i0[0x10]; unsigned char o[0x10]; int main() { - int k =3D 0; - asm("mov r2, %0\n" - "ldr r0, [r2]\n"::"r"((char *)(i0)));; - asm("vmsr fpscr, r0"); - asm("mov r2, %0\n" - "vmrs r4, fpscr\n" - "str r4, [r2]\n"::"r"((char *)(o)));; - for (k =3D 0; k < 0x10; k++) - printf("%02x", o[0x10 - 1 - k]); - printf("\n"); + =C2=A0=C2=A0=C2=A0=C2=A0int k =3D 0; + =C2=A0=C2=A0=C2=A0=C2=A0asm("mov r2, %0\n" + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"ldr r0, [r2]\n"::"r"((ch= ar *)(i0)));; + =C2=A0=C2=A0=C2=A0=C2=A0asm("vmsr fpscr, r0"); + =C2=A0=C2=A0=C2=A0=C2=A0asm("mov r2, %0\n" + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"vmrs r4, fpscr\n" + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"str r4, [r2]\n"::"r"((ch= ar *)(o)));; + =C2=A0=C2=A0=C2=A0=C2=A0for (k =3D 0; k < 0x10; k++) + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0printf("%02x", o[0x10 - 1= - k]); + =C2=A0=C2=A0=C2=A0=C2=A0printf("\n"); } unsigned char i0[0x10] =3D {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x0= 0, 0x28, 0x1c, 0xc7, 0x01, 0x00, 0x00, 0x00, 0x00}; = /*********** End fo the bug **********/ = When the program is compiled into arm binary code and running on a real arm machine, and running in qemu, we have the following result = $ arm-linux-gnueabihf-gcc arm.c -o arm -static $ ./arm 000000000000000000000000fff7009f $ qemu-arm arm 000000000000000000000000ffffffff = According to the ARM manual, bits[19, 14:13, 6:5] of FPSCR should be reserved as zero. However, arm qemu fails to keep these bits to be zero: these bits can be actually modified in QEMU. = + QEMU version is 2.7.0. The operating system is Linux 3.13.0. x86_64. + = Thanks! -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1641861 Title: fail to correctly emulate FPSCR register on arm Status in QEMU: New Bug description: Hi all, we systematically tested the QEMU implementation for emulating arm user mode programs. We found that QEMU incorrectly emulate the FPSCR register. The following the proof of code: /*********** Beginning of the bug: arm.c **********/ int printf(const char *format, ...); unsigned char i0[0x10]; unsigned char o[0x10]; int main() { =C2=A0=C2=A0=C2=A0=C2=A0int k =3D 0; =C2=A0=C2=A0=C2=A0=C2=A0asm("mov r2, %0\n" =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"ldr r0, [r2]\n"::"r"((ch= ar *)(i0)));; =C2=A0=C2=A0=C2=A0=C2=A0asm("vmsr fpscr, r0"); =C2=A0=C2=A0=C2=A0=C2=A0asm("mov r2, %0\n" =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"vmrs r4, fpscr\n" =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0"str r4, [r2]\n"::"r"((ch= ar *)(o)));; =C2=A0=C2=A0=C2=A0=C2=A0for (k =3D 0; k < 0x10; k++) =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0printf("%02x", o[0x10 - 1= - k]); =C2=A0=C2=A0=C2=A0=C2=A0printf("\n"); } unsigned char i0[0x10] =3D {0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x0= 0, 0x28, 0x1c, 0xc7, 0x01, 0x00, 0x00, 0x00, 0x00}; /*********** End fo the bug **********/ When the program is compiled into arm binary code and running on a real arm machine, and running in qemu, we have the following result $ arm-linux-gnueabihf-gcc arm.c -o arm -static $ ./arm 000000000000000000000000fff7009f $ qemu-arm arm 000000000000000000000000ffffffff According to the ARM manual, bits[19, 14:13, 6:5] of FPSCR should be reserved as zero. However, arm qemu fails to keep these bits to be zero: these bits can be actually modified in QEMU. QEMU version is 2.7.0. The operating system is Linux 3.13.0. x86_64. Thanks! To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1641861/+subscriptions