From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56675) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1c9QIK-0003Cn-3H for qemu-devel@nongnu.org; Wed, 23 Nov 2016 00:40:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1c9QIG-00026R-Vv for qemu-devel@nongnu.org; Wed, 23 Nov 2016 00:40:32 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:41718 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1c9QIG-00025X-PO for qemu-devel@nongnu.org; Wed, 23 Nov 2016 00:40:28 -0500 Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.17/8.16.0.17) with SMTP id uAN5coQa128582 for ; Wed, 23 Nov 2016 00:40:27 -0500 Received: from e28smtp02.in.ibm.com (e28smtp02.in.ibm.com [125.16.236.2]) by mx0b-001b2d01.pphosted.com with ESMTP id 26w3tyxf4g-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 23 Nov 2016 00:40:27 -0500 Received: from localhost by e28smtp02.in.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Wed, 23 Nov 2016 11:10:23 +0530 Date: Wed, 23 Nov 2016 11:10:08 +0530 From: Bharata B Rao Reply-To: bharata@linux.vnet.ibm.com References: <1479815165-31059-1-git-send-email-nikunj@linux.vnet.ibm.com> <1479815165-31059-3-git-send-email-nikunj@linux.vnet.ibm.com> <20161123040118.GK28479@umbus.fritz.box> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20161123040118.GK28479@umbus.fritz.box> Message-Id: <20161123054008.GC3550@in.ibm.com> Subject: Re: [Qemu-devel] [PATCH 2/9] target-ppc: Fix xscmpodp and xscmpudp instructions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson Cc: Nikunj A Dadhania , qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org On Wed, Nov 23, 2016 at 03:01:18PM +1100, David Gibson wrote: > On Tue, Nov 22, 2016 at 05:15:58PM +0530, Nikunj A Dadhania wrote: > > From: Bharata B Rao > > > > - xscmpodp & xscmpudp are missing flags reset. > > - In xscmpodp, VXCC should be set only if VE is 0 for signalling NaN case > > and VXCC should be set by explicitly checking for quiet NaN case. > > - Comparison is being done only if the operands are not NaNs. However as > > per ISA, it should be done even when operands are NaNs. > > For my interest, can you explain the difference between ordered and > unordered comparisons? I looked at the ISA and mostly just became > confused. >>From another section of the same ISA doc, I see these description which makes the distinction between ordered and unordered comparisions a bit more clear. Unordered: "If either of the operands is a NaN, either quiet or signal- ing, then CR field BF and the FPCC are set to reflect unordered. If either of the operands is a Signaling NaN, then VXSNAN is set." Ordered: "If either of the operands is a NaN, either quiet or signal- ing, then CR field BF and the FPCC are set to reflect unordered. If either of the operands is a Signaling NaN, then VXSNAN is set and, if Invalid Operation is dis- abled (VE=0), VXVC is set. If neither operand is a Sig- naling NaN but at least one operand is a Quiet NaN, then VXVC is set." > > > > > Signed-off-by: Bharata B Rao > > Signed-off-by: Nikunj A Dadhania > > --- > > target-ppc/fpu_helper.c | 41 +++++++++++++++++++++++++---------------- > > 1 file changed, 25 insertions(+), 16 deletions(-) > > > > diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c > > index d3741b4..3027003 100644 > > --- a/target-ppc/fpu_helper.c > > +++ b/target-ppc/fpu_helper.c > > @@ -2410,29 +2410,38 @@ void helper_##op(CPUPPCState *env, uint32_t opcode) \ > > { \ > > ppc_vsr_t xa, xb; \ > > uint32_t cc = 0; \ > > + bool vxsnan_flag = false, vxvc_flag = false; \ > > \ > > + helper_reset_fpstatus(env); \ > > getVSR(xA(opcode), &xa, env); \ > > getVSR(xB(opcode), &xb, env); \ > > \ > > - if (unlikely(float64_is_any_nan(xa.VsrD(0)) || \ > > - float64_is_any_nan(xb.VsrD(0)))) { \ > > - if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \ > > - float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \ > > - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXSNAN, 0); \ > > - } \ > > - if (ordered) { \ > > - float_invalid_op_excp(env, POWERPC_EXCP_FP_VXVC, 0); \ > > + if (float64_is_signaling_nan(xa.VsrD(0), &env->fp_status) || \ > > + float64_is_signaling_nan(xb.VsrD(0), &env->fp_status)) { \ > > + vxsnan_flag = true; \ > > + cc = 1; \ > > + if (fpscr_ve == 0 && ordered) { \ > > + vxvc_flag = true; \ > > } \ > > + } else if ((float64_is_quiet_nan(xa.VsrD(0), &env->fp_status) || \ > > + float64_is_quiet_nan(xb.VsrD(0), &env->fp_status)) \ > > + && ordered) { \ > > cc = 1; \ > > Since you're basically rewriting this, could you please change it to > use symbolic constants for the CC bits, which will make it easier to > follow. Sure will do. Regards, Bharata.