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Violators will be prosecuted for from ; Tue, 22 Nov 2016 23:04:49 -0700 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable From: Michael Roth In-Reply-To: <20161123051009.GF17795@umbus.fritz.box> References: <1479869383-16162-1-git-send-email-david@gibson.dropbear.id.au> <1479869383-16162-8-git-send-email-david@gibson.dropbear.id.au> <20161123051009.GF17795@umbus.fritz.box> Date: Wed, 23 Nov 2016 00:04:39 -0600 Message-Id: <20161123060439.3756.38695@loki> Subject: Re: [Qemu-devel] [PULL 07/11] target-ppc: Fix CPU migration from qemu-2.6 <-> later versions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , peter.maydell@linaro.org, stefanha@redhat.com Cc: agraf@suse.de, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Quoting David Gibson (2016-11-22 23:10:09) > On Wed, Nov 23, 2016 at 01:49:39PM +1100, David Gibson wrote: > > When migration for target-ppc was converted to vmstate, several > > VMSTATE_EQUAL() checks were foolishly included of things that really > > should be internal state. Specifically we verified equality of the > > insns_flags and insns_flags2 fields, which are used within TCG to > > determine which groups of instructions are available on this cpu > > model. Between qemu-2.6 and qemu-2.7 we made some changes to these > > classes which broke migration. > > = > > This path fixes migration both forwards and backwards. On migration > > from 2.6 to later versions we import the fields into teporary > > variables, which we then ignore. In migration backwards, we populate > > the temporary fields from the runtime fields, but mask out the bits > > which were added after qemu-2.6, allowing the VMSTATE_EQUAL in > > qemu-2.6 to accept the stream. > = > Mike, > = > This patch (alone) should also be applied to the v2.7 stable branch to > fix the v2.6<->v2.7 migration failure. When I tried yesterday the > patch applied clean to v2.7.0, so it shouldn't need reworking. > = > Would you like me to resend specifically for the stable branch, or are > you happy to just pick it up from here? I can pick it up from here. > = > > = > > Signed-off-by: David Gibson > > Reviewed-by: Dr. David Alan Gilbert > > Reviewed-by: Thomas Huth > > Reviewed-by: Greg Kurz > > --- > > target-ppc/cpu.h | 6 ++++++ > > target-ppc/machine.c | 29 +++++++++++++++++++++++++---- > > 2 files changed, 31 insertions(+), 4 deletions(-) > > = > > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > > index 1c90adb..7798b2e 100644 > > --- a/target-ppc/cpu.h > > +++ b/target-ppc/cpu.h > > @@ -1166,6 +1166,12 @@ struct PowerPCCPU { > > int cpu_dt_id; > > uint32_t max_compat; > > uint32_t cpu_version; > > + > > + /* fields used only during migration for compatibility hacks */ > > + target_ulong mig_msr_mask; > > + uint64_t mig_insns_flags; > > + uint64_t mig_insns_flags2; > > + uint32_t mig_nb_BATs; > > }; > > = > > static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) > > diff --git a/target-ppc/machine.c b/target-ppc/machine.c > > index e43cb6c..fcac263 100644 > > --- a/target-ppc/machine.c > > +++ b/target-ppc/machine.c > > @@ -140,6 +140,21 @@ static void cpu_pre_save(void *opaque) > > PowerPCCPU *cpu =3D opaque; > > CPUPPCState *env =3D &cpu->env; > > int i; > > + uint64_t insns_compat_mask =3D > > + PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB > > + | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES > > + | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES > > + | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT > > + | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ > > + | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSY= NC > > + | PPC_64B | PPC_64BX | PPC_ALTIVEC > > + | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; > > + uint64_t insns_compat_mask2 =3D PPC2_VSX | PPC2_VSX207 | PPC2_DFP = | PPC2_DBRX > > + | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 > > + | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 > > + | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 > > + | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 > > + | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; > > = > > env->spr[SPR_LR] =3D env->lr; > > env->spr[SPR_CTR] =3D env->ctr; > > @@ -161,6 +176,12 @@ static void cpu_pre_save(void *opaque) > > env->spr[SPR_IBAT4U + 2*i] =3D env->IBAT[0][i+4]; > > env->spr[SPR_IBAT4U + 2*i + 1] =3D env->IBAT[1][i+4]; > > } > > + > > + /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ > > + cpu->mig_msr_mask =3D env->msr_mask; > > + cpu->mig_insns_flags =3D env->insns_flags & insns_compat_mask; > > + cpu->mig_insns_flags2 =3D env->insns_flags2 & insns_compat_mask2; > > + cpu->mig_nb_BATs =3D env->nb_BATs; > > } > > = > > static int cpu_post_load(void *opaque, int version_id) > > @@ -561,10 +582,10 @@ const VMStateDescription vmstate_ppc_cpu =3D { > > /* FIXME: access_type? */ > > = > > /* Sanity checking */ > > - VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU), > > - VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU), > > - VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU), > > - VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU), > > + VMSTATE_UINTTL(mig_msr_mask, PowerPCCPU), > > + VMSTATE_UINT64(mig_insns_flags, PowerPCCPU), > > + VMSTATE_UINT64(mig_insns_flags2, PowerPCCPU), > > + VMSTATE_UINT32(mig_nb_BATs, PowerPCCPU), > > VMSTATE_END_OF_LIST() > > }, > > .subsections =3D (const VMStateDescription*[]) { > = > -- = > David Gibson | I'll have my music baroque, and my code > david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _othe= r_ > | _way_ _around_! > http://www.ozlabs.org/~dgibson