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From: David Gibson <david@gibson.dropbear.id.au>
To: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
	nikunj@linux.vnet.ibm.com, bharata@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [PATCH v2 1/4] target-ppc: Implement bcdcfsq. instruction
Date: Thu, 24 Nov 2016 12:18:19 +1100	[thread overview]
Message-ID: <20161124011819.GL17795@umbus.fritz.box> (raw)
In-Reply-To: <1479918105-15616-2-git-send-email-joserz@linux.vnet.ibm.com>

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On Wed, Nov 23, 2016 at 02:21:42PM -0200, Jose Ricardo Ziviani wrote:
> bcdcfsq.: Decimal convert from signed quadword. It is not possible
> to convert values less than 10^31-1 or greater than -10^31-1 to be
> represented in packed decimal format.

You have your less than / greater than the wrong way around in the
above.

> 
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
>  target-ppc/helper.h                 |  1 +
>  target-ppc/int_helper.c             | 45 +++++++++++++++++++++++++++++++++++++
>  target-ppc/translate/vmx-impl.inc.c |  7 ++++++
>  3 files changed, 53 insertions(+)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index da00f0a..87f533c 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -382,6 +382,7 @@ DEF_HELPER_3(bcdcfn, i32, avr, avr, i32)
>  DEF_HELPER_3(bcdctn, i32, avr, avr, i32)
>  DEF_HELPER_3(bcdcfz, i32, avr, avr, i32)
>  DEF_HELPER_3(bcdctz, i32, avr, avr, i32)
> +DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
>  
>  DEF_HELPER_2(xsadddp, void, env, i32)
>  DEF_HELPER_2(xssubdp, void, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 8886a72..751909c 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2874,6 +2874,51 @@ uint32_t helper_bcdctz(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
>      return cr;
>  }
>  
> +uint32_t helper_bcdcfsq(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
> +{
> +    int cr;
> +    int i;
> +    int ox_flag = 0;
> +    uint64_t lo_value;
> +    uint64_t hi_value;
> +    uint64_t max = 0x38d7ea4c68000;

In this case it would be clearer what's going on if you gave this
constant in decimal. "max" is also not a great name - see below.

> +    ppc_avr_t ret = { .u64 = { 0, 0 } };
> +
> +    if (b->s64[HI_IDX] < 0) {
> +        lo_value = -b->s64[LO_IDX];
> +        hi_value = ~b->u64[HI_IDX] + !lo_value;
> +        bcd_put_digit(&ret, 0xD, 0);
> +    } else {
> +        lo_value = b->u64[LO_IDX];
> +        hi_value = b->u64[HI_IDX];
> +        bcd_put_digit(&ret, bcd_preferred_sgn(0, ps), 0);
> +    }
> +
> +    if (divu128(&lo_value, &hi_value, max)) {
> +        ox_flag = 1;
> +    } else if (lo_value >= max && hi_value == 0) {

This isn't right.  max == 10^15, but in fact the dividend can safely
be up to 10^16 - 1.  I don't see what checking the remainder against 0
has to do with anything, either.  No overflow + (dividend < 10^16)
should be sufficient.

> +        ox_flag = 1;
> +    }
> +
> +    for (i = 1; hi_value; hi_value /= 10, i++) {
> +        bcd_put_digit(&ret, hi_value % 10, i);
> +    }
> +
> +    for (; lo_value; lo_value /= 10, i++) {
> +        bcd_put_digit(&ret, lo_value % 10, i);
> +    }
> +
> +    cr = bcd_cmp_zero(&ret);
> +
> +    if (unlikely(ox_flag)) {
> +        cr |= 1 << CRF_SO;

Since you posted I've merged a patch from Nikunj which chanes the
meaning of these CRF_* flags to be bit masks instead of shifts.  So
this will need to become just
	cr |= CRF_SO;

> +    }
> +
> +    *r = ret;
> +
> +    return cr;
> +}
> +
>  void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
>  {
>      int i;
> diff --git a/target-ppc/translate/vmx-impl.inc.c b/target-ppc/translate/vmx-impl.inc.c
> index 7143eb3..36141e5 100644
> --- a/target-ppc/translate/vmx-impl.inc.c
> +++ b/target-ppc/translate/vmx-impl.inc.c
> @@ -989,10 +989,14 @@ GEN_BCD2(bcdcfn)
>  GEN_BCD2(bcdctn)
>  GEN_BCD2(bcdcfz)
>  GEN_BCD2(bcdctz)
> +GEN_BCD2(bcdcfsq)
>  
>  static void gen_xpnd04_1(DisasContext *ctx)
>  {
>      switch (opc4(ctx->opcode)) {
> +    case 2:
> +        gen_bcdcfsq(ctx);
> +        break;
>      case 4:
>          gen_bcdctz(ctx);
>          break;
> @@ -1014,6 +1018,9 @@ static void gen_xpnd04_1(DisasContext *ctx)
>  static void gen_xpnd04_2(DisasContext *ctx)
>  {
>      switch (opc4(ctx->opcode)) {
> +    case 2:
> +        gen_bcdcfsq(ctx);
> +        break;
>      case 4:
>          gen_bcdctz(ctx);
>          break;

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  parent reply	other threads:[~2016-11-24  1:28 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-11-23 16:21 [Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part II Jose Ricardo Ziviani
2016-11-23 16:21 ` [Qemu-devel] [PATCH v2 1/4] target-ppc: Implement bcdcfsq. instruction Jose Ricardo Ziviani
2016-11-24  0:43   ` Richard Henderson
2016-11-24  1:20     ` David Gibson
2016-11-24 16:31     ` [Qemu-devel] [Qemu-ppc] " joserz
2016-11-24 22:16       ` David Gibson
2016-11-24  1:18   ` David Gibson [this message]
2016-11-23 16:21 ` [Qemu-devel] [PATCH v2 2/4] target-ppc: Implement bcdctsq. instruction Jose Ricardo Ziviani
2016-11-24  1:24   ` David Gibson
2016-11-23 16:21 ` [Qemu-devel] [PATCH v2 3/4] target-ppc: Implement bcdcpsgn. instruction Jose Ricardo Ziviani
2016-11-24  1:26   ` David Gibson
2016-11-23 16:21 ` [Qemu-devel] [PATCH v2 4/4] target-ppc: Implement bcdsetsgn. instruction Jose Ricardo Ziviani
2016-11-24  1:27   ` David Gibson
2016-11-24  1:28 ` [Qemu-devel] [PATCH v2 0/4] POWER9 TCG enablements - BCD functions part II David Gibson
2016-11-24 16:36   ` [Qemu-devel] [Qemu-ppc] " joserz

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