* [Qemu-devel] [PATCH v1 1/9] target-ppc: implement lxvl instruction
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
@ 2016-12-07 18:24 ` Nikunj A Dadhania
2016-12-08 22:25 ` David Gibson
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 2/9] target-ppc: implement lxvll instruction Nikunj A Dadhania
` (7 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
lxvl: Load VSX Vector with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes results in:
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/mem_helper.c | 33 +++++++++++++++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 62 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index bc39efb..d9ccafd 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -317,6 +317,7 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
DEF_HELPER_3(stvebx, void, env, avr, tl)
DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
+DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 1ab8a6e..54447a7 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -24,6 +24,7 @@
#include "helper_regs.h"
#include "exec/cpu_ldst.h"
+#include "internal.h"
//#define DEBUG_OP
@@ -284,8 +285,40 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
#undef I
#undef LVE
+#ifdef TARGET_PPC64
+#define GET_NB(rb) ((rb >> 56) & 0xFF)
+#else
+#define GET_NB(rb) ((rb >> 24) & 0xFF)
+#endif
+
+void helper_lxvl(CPUPPCState *env, target_ulong addr,
+ target_ulong xt_num, target_ulong rb)
+{
+ int i;
+ ppc_vsr_t xt;
+ uint64_t nb = GET_NB(rb);
+
+ xt.s128 = int128_zero();
+ if (nb) {
+ nb = (nb >= 16) ? 16 : nb;
+ if (msr_le) {
+ for (i = 16; i > 16 - nb; i--) {
+ xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ } else {
+ for (i = 0; i < nb; i++) {
+ xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ }
+ }
+ putVSR(xt_num, &xt, env);
+}
+
#undef HI_IDX
#undef LO_IDX
+#undef GET_NB
void helper_tbegin(CPUPPCState *env)
{
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 808ee48..6bd70a0 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -240,6 +240,33 @@ VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0)
VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1)
VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
+#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv EA, xt; \
+ \
+ if (xT(ctx->opcode) < 32) { \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ } else { \
+ if (unlikely(!ctx->altivec_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VPU); \
+ return; \
+ } \
+ } \
+ EA = tcg_temp_new(); \
+ xt = tcg_const_tl(xT(ctx->opcode)); \
+ gen_set_access_type(ctx, ACCESS_INT); \
+ gen_addr_register(ctx, EA); \
+ gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
+ tcg_temp_free(EA); \
+ tcg_temp_free(xt); \
+}
+
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index daf6a56..4940ab2 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -10,6 +10,7 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/9] target-ppc: implement lxvl instruction
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 1/9] target-ppc: implement lxvl instruction Nikunj A Dadhania
@ 2016-12-08 22:25 ` David Gibson
2016-12-09 5:54 ` Nikunj A Dadhania
0 siblings, 1 reply; 19+ messages in thread
From: David Gibson @ 2016-12-08 22:25 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 6982 bytes --]
On Wed, Dec 07, 2016 at 11:54:54PM +0530, Nikunj A Dadhania wrote:
> lxvl: Load VSX Vector with Length
>
> Little/Big-endian Storage:
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>
> Loading 14 bytes results in:
>
> Vector (8-bit elements) in BE:
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>
> Vector (8-bit elements) in LE:
> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> |00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Took a while to wrap my head around the semantics, but I believe this
is correct. However, there are a couple of nits:
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/mem_helper.c | 33 +++++++++++++++++++++++++++++++++
> target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
> target-ppc/translate/vsx-ops.inc.c | 1 +
> 4 files changed, 62 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index bc39efb..d9ccafd 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -317,6 +317,7 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
> DEF_HELPER_3(stvebx, void, env, avr, tl)
> DEF_HELPER_3(stvehx, void, env, avr, tl)
> DEF_HELPER_3(stvewx, void, env, avr, tl)
> +DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
> DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
> DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
> DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
> diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
> index 1ab8a6e..54447a7 100644
> --- a/target-ppc/mem_helper.c
> +++ b/target-ppc/mem_helper.c
> @@ -24,6 +24,7 @@
>
> #include "helper_regs.h"
> #include "exec/cpu_ldst.h"
> +#include "internal.h"
>
> //#define DEBUG_OP
>
> @@ -284,8 +285,40 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
> #undef I
> #undef LVE
>
> +#ifdef TARGET_PPC64
> +#define GET_NB(rb) ((rb >> 56) & 0xFF)
> +#else
> +#define GET_NB(rb) ((rb >> 24) & 0xFF)
> +#endif
A 32-bit VSX implementation seems... improbable. Simpler to just
bracket the whole thing with ifdef TARGET_PPC64.
> +
> +void helper_lxvl(CPUPPCState *env, target_ulong addr,
> + target_ulong xt_num, target_ulong rb)
I think it would be nicer to either have two different helpers for the
LE and BE cases, or take an endian parameter. That should allow you
to share the helper with the lxvll implementation.
> +{
> + int i;
> + ppc_vsr_t xt;
> + uint64_t nb = GET_NB(rb);
> +
> + xt.s128 = int128_zero();
> + if (nb) {
> + nb = (nb >= 16) ? 16 : nb;
> + if (msr_le) {
> + for (i = 16; i > 16 - nb; i--) {
> + xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC());
> + addr = addr_add(env, addr, 1);
> + }
> + } else {
> + for (i = 0; i < nb; i++) {
> + xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC());
> + addr = addr_add(env, addr, 1);
> + }
> + }
> + }
> + putVSR(xt_num, &xt, env);
> +}
> +
> #undef HI_IDX
> #undef LO_IDX
> +#undef GET_NB
>
> void helper_tbegin(CPUPPCState *env)
> {
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index 808ee48..6bd70a0 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -240,6 +240,33 @@ VSX_VECTOR_LOAD_STORE(stxv, st_i64, 0)
> VSX_VECTOR_LOAD_STORE(lxvx, ld_i64, 1)
> VSX_VECTOR_LOAD_STORE(stxvx, st_i64, 1)
>
> +#define VSX_VECTOR_LOAD_STORE_LENGTH(name) \
> +static void gen_##name(DisasContext *ctx) \
> +{ \
> + TCGv EA, xt; \
> + \
> + if (xT(ctx->opcode) < 32) { \
> + if (unlikely(!ctx->vsx_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
> + return; \
> + } \
> + } else { \
> + if (unlikely(!ctx->altivec_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VPU); \
> + return; \
> + } \
> + } \
> + EA = tcg_temp_new(); \
> + xt = tcg_const_tl(xT(ctx->opcode)); \
> + gen_set_access_type(ctx, ACCESS_INT); \
> + gen_addr_register(ctx, EA); \
> + gen_helper_##name(cpu_env, EA, xt, cpu_gpr[rB(ctx->opcode)]); \
> + tcg_temp_free(EA); \
> + tcg_temp_free(xt); \
> +}
> +
> +VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
> +
> #define VSX_LOAD_SCALAR_DS(name, operation) \
> static void gen_##name(DisasContext *ctx) \
> { \
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index daf6a56..4940ab2 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -10,6 +10,7 @@ GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
> +GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
>
> GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 1/9] target-ppc: implement lxvl instruction
2016-12-08 22:25 ` David Gibson
@ 2016-12-09 5:54 ` Nikunj A Dadhania
0 siblings, 0 replies; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 5:54 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, rth, qemu-devel, bharata
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Dec 07, 2016 at 11:54:54PM +0530, Nikunj A Dadhania wrote:
>> lxvl: Load VSX Vector with Length
>>
>> Little/Big-endian Storage:
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>>
>> Loading 14 bytes results in:
>>
>> Vector (8-bit elements) in BE:
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>>
>> Vector (8-bit elements) in LE:
>> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>> |00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
>> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>
> Took a while to wrap my head around the semantics, but I believe this
> is correct. However, there are a couple of nits:
>
>>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> target-ppc/helper.h | 1 +
>> target-ppc/mem_helper.c | 33 +++++++++++++++++++++++++++++++++
>> target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
>> target-ppc/translate/vsx-ops.inc.c | 1 +
>> 4 files changed, 62 insertions(+)
>>
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index bc39efb..d9ccafd 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -317,6 +317,7 @@ DEF_HELPER_3(lvewx, void, env, avr, tl)
>> DEF_HELPER_3(stvebx, void, env, avr, tl)
>> DEF_HELPER_3(stvehx, void, env, avr, tl)
>> DEF_HELPER_3(stvewx, void, env, avr, tl)
>> +DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
>> DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
>> DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
>> DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
>> diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
>> index 1ab8a6e..54447a7 100644
>> --- a/target-ppc/mem_helper.c
>> +++ b/target-ppc/mem_helper.c
>> @@ -24,6 +24,7 @@
>>
>> #include "helper_regs.h"
>> #include "exec/cpu_ldst.h"
>> +#include "internal.h"
>>
>> //#define DEBUG_OP
>>
>> @@ -284,8 +285,40 @@ STVE(stvewx, cpu_stl_data_ra, bswap32, u32)
>> #undef I
>> #undef LVE
>>
>> +#ifdef TARGET_PPC64
>> +#define GET_NB(rb) ((rb >> 56) & 0xFF)
>> +#else
>> +#define GET_NB(rb) ((rb >> 24) & 0xFF)
>> +#endif
>
> A 32-bit VSX implementation seems... improbable. Simpler to just
> bracket the whole thing with ifdef TARGET_PPC64.
Sure, can be done, just that the instruction specifically got bit 0:7, i
thought that I shouldn't limit my implementation to just PPC64.
>> +
>> +void helper_lxvl(CPUPPCState *env, target_ulong addr,
>> + target_ulong xt_num, target_ulong rb)
>
> I think it would be nicer to either have two different helpers for the
> LE and BE cases, or take an endian parameter. That should allow you
> to share the helper with the lxvll implementation.
Something like the below should work:
#define VSX_LXVL(name, lj) \
void helper_##name(CPUPPCState *env, target_ulong addr, \
target_ulong xt_num, target_ulong rb) \
{ \
int i; \
ppc_vsr_t xt; \
uint64_t nb = GET_NB(rb); \
\
xt.s128 = int128_zero(); \
if (nb) { \
nb = (nb >= 16) ? 16 : nb; \
if (msr_le && !lj) { \
for (i = 16; i > 16 - nb; i--) { \
xt.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
addr = addr_add(env, addr, 1); \
} \
} else { \
for (i = 0; i < nb; i++) { \
xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC()); \
addr = addr_add(env, addr, 1); \
} \
} \
} \
putVSR(xt_num, &xt, env); \
}
VSX_LXVL(lxvl, 0)
VSX_LXVL(lxvll, 1)
Regards
Nikunj
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v1 2/9] target-ppc: implement lxvll instruction
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 1/9] target-ppc: implement lxvl instruction Nikunj A Dadhania
@ 2016-12-07 18:24 ` Nikunj A Dadhania
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction Nikunj A Dadhania
` (6 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
lxvll: Load VSX Vector Left-justified with Length
Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Loading 14 bytes to vector (8-bit elements) in BE/LE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/mem_helper.c | 18 ++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 1 +
target-ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 21 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index d9ccafd..67c8b71 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -318,6 +318,7 @@ DEF_HELPER_3(stvebx, void, env, avr, tl)
DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
+DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 54447a7..08fd90d 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -316,6 +316,24 @@ void helper_lxvl(CPUPPCState *env, target_ulong addr,
putVSR(xt_num, &xt, env);
}
+void helper_lxvll(CPUPPCState *env, target_ulong addr,
+ target_ulong xt_num, target_ulong rb)
+{
+ int i;
+ ppc_vsr_t xt;
+ uint64_t nb = GET_NB(rb);
+
+ xt.s128 = int128_zero();
+ if (nb) {
+ nb = (nb >= 16) ? 16 : nb;
+ for (i = 0; i < nb; i++) {
+ xt.VsrB(i) = cpu_ldub_data_ra(env, addr, GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ }
+ putVSR(xt_num, &xt, env);
+}
+
#undef HI_IDX
#undef LO_IDX
#undef GET_NB
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 6bd70a0..ee884cf 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -266,6 +266,7 @@ static void gen_##name(DisasContext *ctx) \
}
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
+VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 4940ab2..88f46d9 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -11,6 +11,7 @@ GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvx, 0x1F, 0x0C, 0x08, 0x00000040, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(lxvl, 0x1F, 0x0D, 0x08, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(lxvll, 0x1F, 0x0D, 0x09, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 1/9] target-ppc: implement lxvl instruction Nikunj A Dadhania
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 2/9] target-ppc: implement lxvll instruction Nikunj A Dadhania
@ 2016-12-07 18:24 ` Nikunj A Dadhania
2016-12-08 22:26 ` David Gibson
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 4/9] target-ppc: implement stxvll instructions Nikunj A Dadhania
` (5 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
stxvl: Store VSX Vector with Length
Vector (8-bit elements) in BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Vector (8-bit elements) in LE:
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
|00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
+--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
Storing 14 bytes would result in following Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/mem_helper.c | 25 +++++++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 1 +
target-ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 28 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 67c8b71..5ddc96d 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -319,6 +319,7 @@ DEF_HELPER_3(stvehx, void, env, avr, tl)
DEF_HELPER_3(stvewx, void, env, avr, tl)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
+DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 08fd90d..771c660 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -334,6 +334,31 @@ void helper_lxvll(CPUPPCState *env, target_ulong addr,
putVSR(xt_num, &xt, env);
}
+void helper_stxvl(CPUPPCState *env, target_ulong addr,
+ target_ulong xt_num, target_ulong rb)
+{
+ int i;
+ ppc_vsr_t xt;
+ target_ulong nb = GET_NB(rb);
+
+ if (!nb) {
+ return;
+ }
+ getVSR(xt_num, &xt, env);
+ nb = (nb >= 16) ? 16 : nb;
+ if (msr_le) {
+ for (i = 16; i > 16 - nb; i--) {
+ cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ } else {
+ for (i = 0; i < nb; i++) {
+ cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+ }
+}
+
#undef HI_IDX
#undef LO_IDX
#undef GET_NB
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index ee884cf..6d61285 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -267,6 +267,7 @@ static void gen_##name(DisasContext *ctx) \
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
+VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 88f46d9..76eba3c 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -23,6 +23,7 @@ GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction Nikunj A Dadhania
@ 2016-12-08 22:26 ` David Gibson
2016-12-09 5:54 ` Nikunj A Dadhania
0 siblings, 1 reply; 19+ messages in thread
From: David Gibson @ 2016-12-08 22:26 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 4586 bytes --]
On Wed, Dec 07, 2016 at 11:54:56PM +0530, Nikunj A Dadhania wrote:
> stxvl: Store VSX Vector with Length
>
> Vector (8-bit elements) in BE:
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>
> Vector (8-bit elements) in LE:
> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
> |00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>
> Storing 14 bytes would result in following Little/Big-endian Storage:
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
As with lxvl/lxvll I think you should be able to share the helper for
stxvl and stxvll.
> ---
> target-ppc/helper.h | 1 +
> target-ppc/mem_helper.c | 25 +++++++++++++++++++++++++
> target-ppc/translate/vsx-impl.inc.c | 1 +
> target-ppc/translate/vsx-ops.inc.c | 1 +
> 4 files changed, 28 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 67c8b71..5ddc96d 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -319,6 +319,7 @@ DEF_HELPER_3(stvehx, void, env, avr, tl)
> DEF_HELPER_3(stvewx, void, env, avr, tl)
> DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
> DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
> +DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
> DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
> DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
> DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
> diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
> index 08fd90d..771c660 100644
> --- a/target-ppc/mem_helper.c
> +++ b/target-ppc/mem_helper.c
> @@ -334,6 +334,31 @@ void helper_lxvll(CPUPPCState *env, target_ulong addr,
> putVSR(xt_num, &xt, env);
> }
>
> +void helper_stxvl(CPUPPCState *env, target_ulong addr,
> + target_ulong xt_num, target_ulong rb)
> +{
> + int i;
> + ppc_vsr_t xt;
> + target_ulong nb = GET_NB(rb);
> +
> + if (!nb) {
> + return;
> + }
> + getVSR(xt_num, &xt, env);
> + nb = (nb >= 16) ? 16 : nb;
> + if (msr_le) {
> + for (i = 16; i > 16 - nb; i--) {
> + cpu_stb_data_ra(env, addr, xt.VsrB(i - 1), GETPC());
> + addr = addr_add(env, addr, 1);
> + }
> + } else {
> + for (i = 0; i < nb; i++) {
> + cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC());
> + addr = addr_add(env, addr, 1);
> + }
> + }
> +}
> +
> #undef HI_IDX
> #undef LO_IDX
> #undef GET_NB
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index ee884cf..6d61285 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -267,6 +267,7 @@ static void gen_##name(DisasContext *ctx) \
>
> VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
> VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
> +VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
>
> #define VSX_LOAD_SCALAR_DS(name, operation) \
> static void gen_##name(DisasContext *ctx) \
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index 88f46d9..76eba3c 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -23,6 +23,7 @@ GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
> GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
> +GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
>
> GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
> GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction
2016-12-08 22:26 ` David Gibson
@ 2016-12-09 5:54 ` Nikunj A Dadhania
0 siblings, 0 replies; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-09 5:54 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, rth, qemu-devel, bharata
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Dec 07, 2016 at 11:54:56PM +0530, Nikunj A Dadhania wrote:
>> stxvl: Store VSX Vector with Length
>>
>> Vector (8-bit elements) in BE:
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>>
>> Vector (8-bit elements) in LE:
>> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>> |00|00|“T”|“S”|“E”|“T”|“ ”|“a”|“ ”|“s”|“i”|“ ”|“s”|“i”|"h"|"T"|
>> +--+--+---+---+---+---+---+---+---+---+---+---+---+---+---+---+
>>
>> Storing 14 bytes would result in following Little/Big-endian Storage:
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>> |“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
>> +---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
>>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>
> As with lxvl/lxvll I think you should be able to share the helper for
> stxvl and stxvll.
Sure, will do that.
Regards
Nikunj
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v1 4/9] target-ppc: implement stxvll instructions
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (2 preceding siblings ...)
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 3/9] target-ppc: implement stxvl instruction Nikunj A Dadhania
@ 2016-12-07 18:24 ` Nikunj A Dadhania
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
` (4 subsequent siblings)
8 siblings, 0 replies; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
stxvll: Store VSX Vector Left-justified with Length
Vector (8-bit elements) in LE/BE:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|00|00|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Storing 14 bytes would result in following Little/Big-endian Storage:
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
|“T”|“h”|“i”|“s”|“ ”|“i”|“s”|“ ”|“a”|“ ”|“T”|“E”|“S”|“T”|FF|FF|
+---+---+---+---+---+---+---+---+---+---+---+---+---+---+--+--+
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/mem_helper.c | 18 ++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 1 +
target-ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 21 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 5ddc96d..91bdfc3 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -320,6 +320,7 @@ DEF_HELPER_3(stvewx, void, env, avr, tl)
DEF_HELPER_4(lxvl, void, env, tl, tl, tl)
DEF_HELPER_4(lxvll, void, env, tl, tl, tl)
DEF_HELPER_4(stxvl, void, env, tl, tl, tl)
+DEF_HELPER_4(stxvll, void, env, tl, tl, tl)
DEF_HELPER_4(vsumsws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum2sws, void, env, avr, avr, avr)
DEF_HELPER_4(vsum4sbs, void, env, avr, avr, avr)
diff --git a/target-ppc/mem_helper.c b/target-ppc/mem_helper.c
index 771c660..c603ef5 100644
--- a/target-ppc/mem_helper.c
+++ b/target-ppc/mem_helper.c
@@ -359,6 +359,24 @@ void helper_stxvl(CPUPPCState *env, target_ulong addr,
}
}
+void helper_stxvll(CPUPPCState *env, target_ulong addr,
+ target_ulong xt_num, target_ulong rb)
+{
+ int i;
+ ppc_vsr_t xt;
+ target_ulong nb = GET_NB(rb);
+
+ if (!nb) {
+ return;
+ }
+ getVSR(xt_num, &xt, env);
+ nb = (nb >= 16) ? 16 : nb;
+ for (i = 0; i < nb; i++) {
+ cpu_stb_data_ra(env, addr, xt.VsrB(i), GETPC());
+ addr = addr_add(env, addr, 1);
+ }
+}
+
#undef HI_IDX
#undef LO_IDX
#undef GET_NB
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 6d61285..c691141 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -268,6 +268,7 @@ static void gen_##name(DisasContext *ctx) \
VSX_VECTOR_LOAD_STORE_LENGTH(lxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(lxvll)
VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
+VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
#define VSX_LOAD_SCALAR_DS(name, operation) \
static void gen_##name(DisasContext *ctx) \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 76eba3c..be446ae 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -24,6 +24,7 @@ GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvx, 0x1F, 0x0C, 0x0C, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(stxvl, 0x1F, 0x0D, 0x0C, 0, PPC_NONE, PPC2_ISA300),
+GEN_HANDLER_E(stxvll, 0x1F, 0x0D, 0x0D, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* [Qemu-devel] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (3 preceding siblings ...)
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 4/9] target-ppc: implement stxvll instructions Nikunj A Dadhania
@ 2016-12-07 18:24 ` Nikunj A Dadhania
2016-12-08 22:32 ` David Gibson
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 6/9] target-ppc: implement xxinsertw instruction Nikunj A Dadhania
` (3 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xxextractuw: VSX Vector Extract Unsigned Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 31 +++++++++++++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
target-ppc/translate/vsx-ops.inc.c | 5 +++++
4 files changed, 64 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 91bdfc3..940f81c 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -536,6 +536,7 @@ DEF_HELPER_2(xvrspic, void, env, i32)
DEF_HELPER_2(xvrspim, void, env, i32)
DEF_HELPER_2(xvrspip, void, env, i32)
DEF_HELPER_2(xvrspiz, void, env, i32)
+DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 7030f61..093c5ec 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2033,6 +2033,37 @@ VEXTRACT(uw, u32)
VEXTRACT(d, u64)
#undef VEXTRACT
+#if defined(HOST_WORDS_BIGENDIAN)
+#define XXEXTRACT(name, element) \
+void helper_##name(CPUPPCState *env, target_ulong xtn, \
+ target_ulong xbn, uint32_t index) \
+{ \
+ ppc_vsr_t xt, xb; \
+ uint32_t es = sizeof(xt.element[0]); \
+ \
+ getVSR(xbn, &xb, env); \
+ memset(&xt, 0, sizeof(xt)); \
+ memcpy(&xt.u8[8 - es], &xb.u8[index], es); \
+ putVSR(xtn, &xt, env); \
+}
+#else
+#define XXEXTRACT(name, element) \
+void helper_##name(CPUPPCState *env, target_ulong xtn, \
+ target_ulong xbn, uint32_t index) \
+{ \
+ ppc_vsr_t xt, xb; \
+ uint32_t es = sizeof(xt.element[0]); \
+ uint32_t s = (16 - index) - es; \
+ \
+ getVSR(xbn, &xb, env); \
+ memset(&xt, 0, sizeof(xt)); \
+ memcpy(&xt.u8[8], &xb.u8[s], es); \
+ putVSR(xtn, &xt, env); \
+}
+#endif
+XXEXTRACT(xxextractuw, u32)
+#undef XXEXTRACT
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index c691141..a9c07c9 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -1162,6 +1162,33 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
+#define VSX_EXTRACT(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv xt, xb; \
+ TCGv_i32 t0 = tcg_temp_new_i32(); \
+ uint8_t uimm = UIMM4(ctx->opcode); \
+ \
+ if (unlikely(!ctx->vsx_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_VSXU); \
+ return; \
+ } \
+ if (uimm > 12) { \
+ tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
+ tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
+ return; \
+ } \
+ xt = tcg_const_tl(xT(ctx->opcode)); \
+ xb = tcg_const_tl(xB(ctx->opcode)); \
+ tcg_gen_movi_i32(t0, uimm); \
+ gen_helper_##name(cpu_env, xt, xb, t0); \
+ tcg_temp_free(xb); \
+ tcg_temp_free(xt); \
+ tcg_temp_free_i32(t0); \
+}
+
+VSX_EXTRACT(xxextractuw)
+
#undef GEN_XX2FORM
#undef GEN_XX3FORM
#undef GEN_XX2IFORM
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index be446ae..3ce657d 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -45,6 +45,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
+#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
+GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
+
#define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
@@ -272,6 +276,7 @@ GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
+GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
@ 2016-12-08 22:32 ` David Gibson
0 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2016-12-08 22:32 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 7136 bytes --]
On Wed, Dec 07, 2016 at 11:54:58PM +0530, Nikunj A Dadhania wrote:
> xxextractuw: VSX Vector Extract Unsigned Word
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 31 +++++++++++++++++++++++++++++++
> target-ppc/translate/vsx-impl.inc.c | 27 +++++++++++++++++++++++++++
> target-ppc/translate/vsx-ops.inc.c | 5 +++++
> 4 files changed, 64 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 91bdfc3..940f81c 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -536,6 +536,7 @@ DEF_HELPER_2(xvrspic, void, env, i32)
> DEF_HELPER_2(xvrspim, void, env, i32)
> DEF_HELPER_2(xvrspip, void, env, i32)
> DEF_HELPER_2(xvrspiz, void, env, i32)
> +DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
>
> DEF_HELPER_2(efscfsi, i32, env, i32)
> DEF_HELPER_2(efscfui, i32, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 7030f61..093c5ec 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2033,6 +2033,37 @@ VEXTRACT(uw, u32)
> VEXTRACT(d, u64)
> #undef VEXTRACT
>
> +#if defined(HOST_WORDS_BIGENDIAN)
> +#define XXEXTRACT(name, element) \
> +void helper_##name(CPUPPCState *env, target_ulong xtn, \
> + target_ulong xbn, uint32_t index) \
You're already breaking out to a helper. Why not just pass the
element size in as a parameter. As a bonus that means you can
restrict the ifdef HOST_WORDS_BIGENDIAN to a couple of lines, instead
of the whole helper.
> +{ \
> + ppc_vsr_t xt, xb; \
> + uint32_t es = sizeof(xt.element[0]); \
Also, strictly speaking, this should be a size_t.
> + getVSR(xbn, &xb, env); \
> + memset(&xt, 0, sizeof(xt)); \
> + memcpy(&xt.u8[8 - es], &xb.u8[index], es); \
> + putVSR(xtn, &xt, env); \
> +}
> +#else
> +#define XXEXTRACT(name, element) \
> +void helper_##name(CPUPPCState *env, target_ulong xtn, \
> + target_ulong xbn, uint32_t index) \
> +{ \
> + ppc_vsr_t xt, xb; \
> + uint32_t es = sizeof(xt.element[0]); \
> + uint32_t s = (16 - index) - es; \
> + \
> + getVSR(xbn, &xb, env); \
> + memset(&xt, 0, sizeof(xt)); \
> + memcpy(&xt.u8[8], &xb.u8[s], es); \
> + putVSR(xtn, &xt, env); \
> +}
> +#endif
> +XXEXTRACT(xxextractuw, u32)
> +#undef XXEXTRACT
> +
> #define VEXT_SIGNED(name, element, mask, cast, recast) \
> void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index c691141..a9c07c9 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -1162,6 +1162,33 @@ static void gen_xxsldwi(DisasContext *ctx)
> tcg_temp_free_i64(xtl);
> }
>
> +#define VSX_EXTRACT(name) \
> +static void gen_##name(DisasContext *ctx) \
> +{ \
> + TCGv xt, xb; \
> + TCGv_i32 t0 = tcg_temp_new_i32(); \
> + uint8_t uimm = UIMM4(ctx->opcode); \
> + \
> + if (unlikely(!ctx->vsx_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_VSXU); \
> + return; \
> + } \
> + if (uimm > 12) { \
> + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); \
> + tcg_gen_movi_i64(cpu_vsrl(xT(ctx->opcode)), 0); \
> + return; \
> + } \
> + xt = tcg_const_tl(xT(ctx->opcode)); \
> + xb = tcg_const_tl(xB(ctx->opcode)); \
> + tcg_gen_movi_i32(t0, uimm); \
> + gen_helper_##name(cpu_env, xt, xb, t0); \
> + tcg_temp_free(xb); \
> + tcg_temp_free(xt); \
> + tcg_temp_free_i32(t0); \
> +}
> +
> +VSX_EXTRACT(xxextractuw)
> +
> #undef GEN_XX2FORM
> #undef GEN_XX3FORM
> #undef GEN_XX2IFORM
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index be446ae..3ce657d 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -45,6 +45,10 @@ GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
> GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
> GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
>
> +#define GEN_XX2FORM_EXT(name, opc2, opc3, fl2) \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0x00100000, PPC_NONE, fl2), \
> +GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0x00100000, PPC_NONE, fl2)
> +
> #define GEN_XX2FORM_EO(name, opc2, opc3, opc4, fl2) \
> GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 0, opc3, opc4, 0, PPC_NONE, fl2), \
> GEN_HANDLER2_E_2(name, #name, 0x3C, opc2 | 1, opc3, opc4, 0, PPC_NONE, fl2)
> @@ -272,6 +276,7 @@ GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
> GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
> GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
> GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
> +GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
>
> #define GEN_XXSEL_ROW(opc3) \
> GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v1 6/9] target-ppc: implement xxinsertw instruction
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (4 preceding siblings ...)
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 5/9] target-ppc: implement xxextractuw instruction Nikunj A Dadhania
@ 2016-12-07 18:24 ` Nikunj A Dadhania
2016-12-08 22:34 ` David Gibson
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 7/9] target-ppc: implement xsnegqp instruction Nikunj A Dadhania
` (2 subsequent siblings)
8 siblings, 1 reply; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:24 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xxinsertw: VSX Vector Insert Word
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 30 ++++++++++++++++++++++++++++++
target-ppc/translate/vsx-impl.inc.c | 5 +++--
target-ppc/translate/vsx-ops.inc.c | 1 +
4 files changed, 35 insertions(+), 2 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 940f81c..9f812c8 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -537,6 +537,7 @@ DEF_HELPER_2(xvrspim, void, env, i32)
DEF_HELPER_2(xvrspip, void, env, i32)
DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
+DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 093c5ec..b6e8c37 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -2064,6 +2064,36 @@ void helper_##name(CPUPPCState *env, target_ulong xtn, \
XXEXTRACT(xxextractuw, u32)
#undef XXEXTRACT
+#if defined(HOST_WORDS_BIGENDIAN)
+#define XXINSERT(name, element) \
+void helper_##name(CPUPPCState *env, target_ulong xtn, \
+ target_ulong xbn, uint32_t index) \
+{ \
+ ppc_vsr_t xt, xb; \
+ \
+ getVSR(xbn, &xb, env); \
+ getVSR(xtn, &xt, env); \
+ memmove(&xt.u8[index], &xb.u8[8 - sizeof(xt.element)], \
+ sizeof(xt.element[0])); \
+ putVSR(xtn, &xt, env); \
+}
+#else
+#define XXINSERT(name, element) \
+void helper_##name(CPUPPCState *env, target_ulong xtn, \
+ target_ulong xbn, uint32_t index) \
+{ \
+ ppc_vsr_t xt, xb; \
+ uint32_t d = (16 - index) - sizeof(xt.element[0]); \
+ \
+ getVSR(xbn, &xb, env); \
+ getVSR(xtn, &xt, env); \
+ memmove(&xt.u8[d], &xb.u8[8], sizeof(xt.element[0])); \
+ putVSR(xtn, &xt, env); \
+}
+#endif
+XXINSERT(xxinsertw, u32)
+#undef XXINSERT
+
#define VEXT_SIGNED(name, element, mask, cast, recast) \
void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
{ \
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index a9c07c9..6a81b2e 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -1162,7 +1162,7 @@ static void gen_xxsldwi(DisasContext *ctx)
tcg_temp_free_i64(xtl);
}
-#define VSX_EXTRACT(name) \
+#define VSX_EXTRACT_INSERT(name) \
static void gen_##name(DisasContext *ctx) \
{ \
TCGv xt, xb; \
@@ -1187,7 +1187,8 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_i32(t0); \
}
-VSX_EXTRACT(xxextractuw)
+VSX_EXTRACT_INSERT(xxextractuw)
+VSX_EXTRACT_INSERT(xxinsertw)
#undef GEN_XX2FORM
#undef GEN_XX3FORM
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 3ce657d..0216efe 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -277,6 +277,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
+GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
#define GEN_XXSEL_ROW(opc3) \
GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 6/9] target-ppc: implement xxinsertw instruction
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 6/9] target-ppc: implement xxinsertw instruction Nikunj A Dadhania
@ 2016-12-08 22:34 ` David Gibson
0 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2016-12-08 22:34 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 5346 bytes --]
On Wed, Dec 07, 2016 at 11:54:59PM +0530, Nikunj A Dadhania wrote:
> xxinsertw: VSX Vector Insert Word
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> Reviewed-by: Richard Henderson <rth@twiddle.net>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 30 ++++++++++++++++++++++++++++++
> target-ppc/translate/vsx-impl.inc.c | 5 +++--
> target-ppc/translate/vsx-ops.inc.c | 1 +
> 4 files changed, 35 insertions(+), 2 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 940f81c..9f812c8 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -537,6 +537,7 @@ DEF_HELPER_2(xvrspim, void, env, i32)
> DEF_HELPER_2(xvrspip, void, env, i32)
> DEF_HELPER_2(xvrspiz, void, env, i32)
> DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
> +DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
>
> DEF_HELPER_2(efscfsi, i32, env, i32)
> DEF_HELPER_2(efscfui, i32, env, i32)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 093c5ec..b6e8c37 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -2064,6 +2064,36 @@ void helper_##name(CPUPPCState *env, target_ulong xtn, \
> XXEXTRACT(xxextractuw, u32)
> #undef XXEXTRACT
>
> +#if defined(HOST_WORDS_BIGENDIAN)
> +#define XXINSERT(name, element) \
> +void helper_##name(CPUPPCState *env, target_ulong xtn, \
> + target_ulong xbn, uint32_t index) \
Again, you should be able to use an element size parameter, rather
than generating multiple helpers.
> +{ \
> + ppc_vsr_t xt, xb; \
> + \
> + getVSR(xbn, &xb, env); \
> + getVSR(xtn, &xt, env); \
> + memmove(&xt.u8[index], &xb.u8[8 - sizeof(xt.element)], \
> + sizeof(xt.element[0]));
> \
You've already copied into the xt and xb temporaries, so memcpy()
should be safe here.
> + putVSR(xtn, &xt, env); \
> +}
> +#else
> +#define XXINSERT(name, element) \
> +void helper_##name(CPUPPCState *env, target_ulong xtn, \
> + target_ulong xbn, uint32_t index) \
> +{ \
> + ppc_vsr_t xt, xb; \
> + uint32_t d = (16 - index) - sizeof(xt.element[0]); \
> + \
> + getVSR(xbn, &xb, env); \
> + getVSR(xtn, &xt, env); \
> + memmove(&xt.u8[d], &xb.u8[8], sizeof(xt.element[0])); \
> + putVSR(xtn, &xt, env); \
> +}
> +#endif
> +XXINSERT(xxinsertw, u32)
> +#undef XXINSERT
> +
> #define VEXT_SIGNED(name, element, mask, cast, recast) \
> void helper_##name(ppc_avr_t *r, ppc_avr_t *b) \
> { \
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index a9c07c9..6a81b2e 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -1162,7 +1162,7 @@ static void gen_xxsldwi(DisasContext *ctx)
> tcg_temp_free_i64(xtl);
> }
>
> -#define VSX_EXTRACT(name) \
> +#define VSX_EXTRACT_INSERT(name) \
> static void gen_##name(DisasContext *ctx) \
> { \
> TCGv xt, xb; \
> @@ -1187,7 +1187,8 @@ static void gen_##name(DisasContext *ctx) \
> tcg_temp_free_i32(t0); \
> }
>
> -VSX_EXTRACT(xxextractuw)
> +VSX_EXTRACT_INSERT(xxextractuw)
> +VSX_EXTRACT_INSERT(xxinsertw)
>
> #undef GEN_XX2FORM
> #undef GEN_XX3FORM
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index 3ce657d..0216efe 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -277,6 +277,7 @@ GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
> GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
> GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
> GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
> +GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
>
> #define GEN_XXSEL_ROW(opc3) \
> GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v1 7/9] target-ppc: implement xsnegqp instruction
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (5 preceding siblings ...)
2016-12-07 18:24 ` [Qemu-devel] [PATCH v1 6/9] target-ppc: implement xxinsertw instruction Nikunj A Dadhania
@ 2016-12-07 18:25 ` Nikunj A Dadhania
2016-12-08 22:50 ` David Gibson
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction Nikunj A Dadhania
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 9/9] target-ppc: Add xxperm and xxpermr instructions Nikunj A Dadhania
8 siblings, 1 reply; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:25 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xsnegqp: VSX Scalar Negate Quad-Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/translate/vsx-impl.inc.c | 4 ++++
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 6a81b2e..01b95df 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -663,6 +663,9 @@ static void glue(gen_, name)(DisasContext *ctx) \
case OP_NABS: \
tcg_gen_or_i64(xbh, xbh, sgm); \
break; \
+ case OP_NEG: \
+ tcg_gen_xor_i64(xbh, xbh, sgm); \
+ break; \
} \
tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
@@ -673,6 +676,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext * ctx) \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 0216efe..d798edb 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -106,6 +106,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
+GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 7/9] target-ppc: implement xsnegqp instruction
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 7/9] target-ppc: implement xsnegqp instruction Nikunj A Dadhania
@ 2016-12-08 22:50 ` David Gibson
0 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2016-12-08 22:50 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 2485 bytes --]
On Wed, Dec 07, 2016 at 11:55:00PM +0530, Nikunj A Dadhania wrote:
> xsnegqp: VSX Scalar Negate Quad-Precision
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Merged to ppc-for-2.9.
> ---
> target-ppc/translate/vsx-impl.inc.c | 4 ++++
> target-ppc/translate/vsx-ops.inc.c | 1 +
> 2 files changed, 5 insertions(+)
>
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index 6a81b2e..01b95df 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -663,6 +663,9 @@ static void glue(gen_, name)(DisasContext *ctx) \
> case OP_NABS: \
> tcg_gen_or_i64(xbh, xbh, sgm); \
> break; \
> + case OP_NEG: \
> + tcg_gen_xor_i64(xbh, xbh, sgm); \
> + break; \
> } \
> tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
> tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
> @@ -673,6 +676,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
>
> VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
> VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
> +VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
>
> #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
> static void glue(gen_, name)(DisasContext * ctx) \
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index 0216efe..d798edb 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -106,6 +106,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
>
> GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
> GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
> +GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
>
> GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
> GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (6 preceding siblings ...)
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 7/9] target-ppc: implement xsnegqp instruction Nikunj A Dadhania
@ 2016-12-07 18:25 ` Nikunj A Dadhania
2016-12-08 22:51 ` David Gibson
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 9/9] target-ppc: Add xxperm and xxpermr instructions Nikunj A Dadhania
8 siblings, 1 reply; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:25 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
xscpsgnqp: VSX Scalar Copy Sign Quad-Precision
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-ppc/translate/vsx-impl.inc.c | 12 +++++++++++-
target-ppc/translate/vsx-ops.inc.c | 1 +
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 01b95df..8321134 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -642,9 +642,10 @@ VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
#define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext *ctx) \
{ \
+ int xa; \
int xt = rD(ctx->opcode) + 32; \
int xb = rB(ctx->opcode) + 32; \
- TCGv_i64 xbh, xbl, sgm; \
+ TCGv_i64 xah, xbh, xbl, sgm; \
\
if (unlikely(!ctx->vsx_enabled)) { \
gen_exception(ctx, POWERPC_EXCP_VSXU); \
@@ -666,6 +667,14 @@ static void glue(gen_, name)(DisasContext *ctx) \
case OP_NEG: \
tcg_gen_xor_i64(xbh, xbh, sgm); \
break; \
+ case OP_CPSGN: \
+ xah = tcg_temp_new_i64(); \
+ xa = rA(ctx->opcode) + 32; \
+ tcg_gen_and_i64(xah, cpu_vsrh(xa), sgm); \
+ tcg_gen_andc_i64(xbh, xbh, sgm); \
+ tcg_gen_or_i64(xbh, xbh, xah); \
+ tcg_temp_free_i64(xah); \
+ break; \
} \
tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
@@ -677,6 +686,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
+VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
#define VSX_VECTOR_MOVE(name, op, sgn_mask) \
static void glue(gen_, name)(DisasContext * ctx) \
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index d798edb..42e83d2 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -107,6 +107,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
+GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction Nikunj A Dadhania
@ 2016-12-08 22:51 ` David Gibson
0 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2016-12-08 22:51 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 3899 bytes --]
On Wed, Dec 07, 2016 at 11:55:01PM +0530, Nikunj A Dadhania wrote:
> xscpsgnqp: VSX Scalar Copy Sign Quad-Precision
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> Reviewed-by: Richard Henderson <rth@twiddle.net>
Merged to ppc-for-2.9
> ---
> target-ppc/translate/vsx-impl.inc.c | 12 +++++++++++-
> target-ppc/translate/vsx-ops.inc.c | 1 +
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index 01b95df..8321134 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -642,9 +642,10 @@ VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
> #define VSX_SCALAR_MOVE_QP(name, op, sgn_mask) \
> static void glue(gen_, name)(DisasContext *ctx) \
> { \
> + int xa; \
> int xt = rD(ctx->opcode) + 32; \
> int xb = rB(ctx->opcode) + 32; \
> - TCGv_i64 xbh, xbl, sgm; \
> + TCGv_i64 xah, xbh, xbl, sgm; \
> \
> if (unlikely(!ctx->vsx_enabled)) { \
> gen_exception(ctx, POWERPC_EXCP_VSXU); \
> @@ -666,6 +667,14 @@ static void glue(gen_, name)(DisasContext *ctx) \
> case OP_NEG: \
> tcg_gen_xor_i64(xbh, xbh, sgm); \
> break; \
> + case OP_CPSGN: \
> + xah = tcg_temp_new_i64(); \
> + xa = rA(ctx->opcode) + 32; \
> + tcg_gen_and_i64(xah, cpu_vsrh(xa), sgm); \
> + tcg_gen_andc_i64(xbh, xbh, sgm); \
> + tcg_gen_or_i64(xbh, xbh, xah); \
> + tcg_temp_free_i64(xah); \
> + break; \
> } \
> tcg_gen_mov_i64(cpu_vsrh(xt), xbh); \
> tcg_gen_mov_i64(cpu_vsrl(xt), xbl); \
> @@ -677,6 +686,7 @@ static void glue(gen_, name)(DisasContext *ctx) \
> VSX_SCALAR_MOVE_QP(xsabsqp, OP_ABS, SGN_MASK_DP)
> VSX_SCALAR_MOVE_QP(xsnabsqp, OP_NABS, SGN_MASK_DP)
> VSX_SCALAR_MOVE_QP(xsnegqp, OP_NEG, SGN_MASK_DP)
> +VSX_SCALAR_MOVE_QP(xscpsgnqp, OP_CPSGN, SGN_MASK_DP)
>
> #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
> static void glue(gen_, name)(DisasContext * ctx) \
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index d798edb..42e83d2 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -107,6 +107,7 @@ GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
> GEN_VSX_XFORM_300_EO(xsabsqp, 0x04, 0x19, 0x00, 0x00000001),
> GEN_VSX_XFORM_300_EO(xsnabsqp, 0x04, 0x19, 0x08, 0x00000001),
> GEN_VSX_XFORM_300_EO(xsnegqp, 0x04, 0x19, 0x10, 0x00000001),
> +GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001),
>
> GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
> GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 19+ messages in thread
* [Qemu-devel] [PATCH v1 9/9] target-ppc: Add xxperm and xxpermr instructions
2016-12-07 18:24 [Qemu-devel] [PATCH v1 ppc-for-2.9 0/9] POWER9 TCG enablements - part9 Nikunj A Dadhania
` (7 preceding siblings ...)
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 8/9] target-ppc: implement xscpsgnqp instruction Nikunj A Dadhania
@ 2016-12-07 18:25 ` Nikunj A Dadhania
2016-12-08 22:51 ` David Gibson
8 siblings, 1 reply; 19+ messages in thread
From: Nikunj A Dadhania @ 2016-12-07 18:25 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, bharata, nikunj
From: Bharata B Rao <bharata@linux.vnet.ibm.com>
xxperm: VSX Vector Permute
xxpermr: VSX Vector Permute Right-indexed
Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/fpu_helper.c | 23 +++++++++++++++++++++++
target-ppc/helper.h | 2 ++
target-ppc/translate/vsx-impl.inc.c | 2 ++
target-ppc/translate/vsx-ops.inc.c | 2 ++
4 files changed, 29 insertions(+)
diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
index 3b867cf..1ccd5e6 100644
--- a/target-ppc/fpu_helper.c
+++ b/target-ppc/fpu_helper.c
@@ -2869,3 +2869,26 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
float_check_status(env);
return xt;
}
+
+#define VSX_XXPERM(op, indexed) \
+void helper_##op(CPUPPCState *env, uint32_t opcode) \
+{ \
+ ppc_vsr_t xt, xa, pcv, xto; \
+ int i, idx; \
+ \
+ getVSR(xA(opcode), &xa, env); \
+ getVSR(xT(opcode), &xt, env); \
+ getVSR(xB(opcode), &pcv, env); \
+ \
+ for (i = 0; i < 16; i++) { \
+ idx = pcv.VsrB(i) & 0x1F; \
+ if (indexed) { \
+ idx = 31 - idx; \
+ } \
+ xto.VsrB(i) = (idx <= 15) ? xa.VsrB(idx) : xt.VsrB(idx - 16); \
+ } \
+ putVSR(xT(opcode), &xto, env); \
+}
+
+VSX_XXPERM(xxperm, 0)
+VSX_XXPERM(xxpermr, 1)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9f812c8..399cf99 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -538,6 +538,8 @@ DEF_HELPER_2(xvrspip, void, env, i32)
DEF_HELPER_2(xvrspiz, void, env, i32)
DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
+DEF_HELPER_2(xxperm, void, env, i32)
+DEF_HELPER_2(xxpermr, void, env, i32)
DEF_HELPER_2(efscfsi, i32, env, i32)
DEF_HELPER_2(efscfui, i32, env, i32)
diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
index 8321134..1d88cee 100644
--- a/target-ppc/translate/vsx-impl.inc.c
+++ b/target-ppc/translate/vsx-impl.inc.c
@@ -913,6 +913,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
+GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
+GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
static void gen_xxbrd(DisasContext *ctx)
{
diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
index 42e83d2..93fb9b8 100644
--- a/target-ppc/translate/vsx-ops.inc.c
+++ b/target-ppc/translate/vsx-ops.inc.c
@@ -275,6 +275,8 @@ VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
+GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
+GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
--
2.7.4
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [Qemu-devel] [PATCH v1 9/9] target-ppc: Add xxperm and xxpermr instructions
2016-12-07 18:25 ` [Qemu-devel] [PATCH v1 9/9] target-ppc: Add xxperm and xxpermr instructions Nikunj A Dadhania
@ 2016-12-08 22:51 ` David Gibson
0 siblings, 0 replies; 19+ messages in thread
From: David Gibson @ 2016-12-08 22:51 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata
[-- Attachment #1: Type: text/plain, Size: 4370 bytes --]
On Wed, Dec 07, 2016 at 11:55:02PM +0530, Nikunj A Dadhania wrote:
> From: Bharata B Rao <bharata@linux.vnet.ibm.com>
>
> xxperm: VSX Vector Permute
> xxpermr: VSX Vector Permute Right-indexed
>
> Signed-off-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Merged to ppc-for-2.9.
> ---
> target-ppc/fpu_helper.c | 23 +++++++++++++++++++++++
> target-ppc/helper.h | 2 ++
> target-ppc/translate/vsx-impl.inc.c | 2 ++
> target-ppc/translate/vsx-ops.inc.c | 2 ++
> 4 files changed, 29 insertions(+)
>
> diff --git a/target-ppc/fpu_helper.c b/target-ppc/fpu_helper.c
> index 3b867cf..1ccd5e6 100644
> --- a/target-ppc/fpu_helper.c
> +++ b/target-ppc/fpu_helper.c
> @@ -2869,3 +2869,26 @@ uint64_t helper_xsrsp(CPUPPCState *env, uint64_t xb)
> float_check_status(env);
> return xt;
> }
> +
> +#define VSX_XXPERM(op, indexed) \
> +void helper_##op(CPUPPCState *env, uint32_t opcode) \
> +{ \
> + ppc_vsr_t xt, xa, pcv, xto; \
> + int i, idx; \
> + \
> + getVSR(xA(opcode), &xa, env); \
> + getVSR(xT(opcode), &xt, env); \
> + getVSR(xB(opcode), &pcv, env); \
> + \
> + for (i = 0; i < 16; i++) { \
> + idx = pcv.VsrB(i) & 0x1F; \
> + if (indexed) { \
> + idx = 31 - idx; \
> + } \
> + xto.VsrB(i) = (idx <= 15) ? xa.VsrB(idx) : xt.VsrB(idx - 16); \
> + } \
> + putVSR(xT(opcode), &xto, env); \
> +}
> +
> +VSX_XXPERM(xxperm, 0)
> +VSX_XXPERM(xxpermr, 1)
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 9f812c8..399cf99 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -538,6 +538,8 @@ DEF_HELPER_2(xvrspip, void, env, i32)
> DEF_HELPER_2(xvrspiz, void, env, i32)
> DEF_HELPER_4(xxextractuw, void, env, tl, tl, i32)
> DEF_HELPER_4(xxinsertw, void, env, tl, tl, i32)
> +DEF_HELPER_2(xxperm, void, env, i32)
> +DEF_HELPER_2(xxpermr, void, env, i32)
>
> DEF_HELPER_2(efscfsi, i32, env, i32)
> DEF_HELPER_2(efscfui, i32, env, i32)
> diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/vsx-impl.inc.c
> index 8321134..1d88cee 100644
> --- a/target-ppc/translate/vsx-impl.inc.c
> +++ b/target-ppc/translate/vsx-impl.inc.c
> @@ -913,6 +913,8 @@ GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
> GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
> GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
> GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
> +GEN_VSX_HELPER_2(xxperm, 0x08, 0x03, 0, PPC2_ISA300)
> +GEN_VSX_HELPER_2(xxpermr, 0x08, 0x07, 0, PPC2_ISA300)
>
> static void gen_xxbrd(DisasContext *ctx)
> {
> diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vsx-ops.inc.c
> index 42e83d2..93fb9b8 100644
> --- a/target-ppc/translate/vsx-ops.inc.c
> +++ b/target-ppc/translate/vsx-ops.inc.c
> @@ -275,6 +275,8 @@ VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
> VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
> GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
> GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
> +GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300),
> +GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300),
> GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
> GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300),
> GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 19+ messages in thread