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From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
	Christoffer Dall <christoffer.dall@linaro.org>,
	Andrew Jones <drjones@redhat.com>
Subject: Re: [Qemu-devel] [PATCH 21/23] hw/arm/virt: Support using SMC for PSCI
Date: Tue, 13 Dec 2016 13:36:35 +0100	[thread overview]
Message-ID: <20161213123635.GL9606@toto> (raw)
In-Reply-To: <1481625384-15077-22-git-send-email-peter.maydell@linaro.org>

On Tue, Dec 13, 2016 at 10:36:22AM +0000, Peter Maydell wrote:
> If we are giving the guest a CPU with EL2, it is likely to
> want to use the HVC instruction itself, for instance for
> providing PSCI to inner guest VMs. This makes using HVC
> as the PSCI conduit for the outer QEMU a bad idea. We will
> want to use SMC instead is this case: this makes sense
> because QEMU's PSCI implementation is effectively an
> emulation of functionality provided by EL3 firmware.
> 
> Add code to support selecting the PSCI conduit to use,
> rather than hardcoding use of HVC.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>


> ---
>  hw/arm/virt.c | 29 ++++++++++++++++++++++-------
>  1 file changed, 22 insertions(+), 7 deletions(-)
> 
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 7adb58b..cce8d2e 100644
> --- a/hw/arm/virt.c
> +++ b/hw/arm/virt.c
> @@ -88,7 +88,7 @@ typedef struct {
>      uint32_t clock_phandle;
>      uint32_t gic_phandle;
>      uint32_t msi_phandle;
> -    bool using_psci;
> +    int psci_conduit;
>  } VirtMachineState;
>  
>  #define TYPE_VIRT_MACHINE   MACHINE_TYPE_NAME("virt")
> @@ -266,9 +266,19 @@ static void fdt_add_psci_node(const VirtMachineState *vms)
>      uint32_t migrate_fn;
>      void *fdt = vms->fdt;
>      ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(0));
> +    const char *psci_method;
>  
> -    if (!vms->using_psci) {
> +    switch (vms->psci_conduit) {
> +    case QEMU_PSCI_CONDUIT_DISABLED:
>          return;
> +    case QEMU_PSCI_CONDUIT_HVC:
> +        psci_method = "hvc";
> +        break;
> +    case QEMU_PSCI_CONDUIT_SMC:
> +        psci_method = "smc";
> +        break;
> +    default:
> +        g_assert_not_reached();
>      }
>  
>      qemu_fdt_add_subnode(fdt, "/psci");
> @@ -300,7 +310,7 @@ static void fdt_add_psci_node(const VirtMachineState *vms)
>       * However, the device tree binding uses 'method' instead, so that is
>       * what we should use here.
>       */
> -    qemu_fdt_setprop_string(fdt, "/psci", "method", "hvc");
> +    qemu_fdt_setprop_string(fdt, "/psci", "method", psci_method);
>  
>      qemu_fdt_setprop_cell(fdt, "/psci", "cpu_suspend", cpu_suspend_fn);
>      qemu_fdt_setprop_cell(fdt, "/psci", "cpu_off", cpu_off_fn);
> @@ -402,7 +412,8 @@ static void fdt_add_cpu_nodes(const VirtMachineState *vms)
>          qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
>                                      armcpu->dtb_compatible);
>  
> -        if (vms->using_psci && vms->smp_cpus > 1) {
> +        if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED
> +            && vms->smp_cpus > 1) {
>              qemu_fdt_setprop_string(vms->fdt, nodename,
>                                          "enable-method", "psci");
>          }
> @@ -1270,7 +1281,11 @@ static void machvirt_init(MachineState *machine)
>       * let the boot ROM sort them out.
>       * The usual case is that we do use QEMU's PSCI implementation.
>       */
> -    vms->using_psci = !(vms->secure && firmware_loaded);
> +    if (vms->secure && firmware_loaded) {
> +        vms->psci_conduit = QEMU_PSCI_CONDUIT_DISABLED;
> +    } else {
> +        vms->psci_conduit = QEMU_PSCI_CONDUIT_HVC;
> +    }
>  
>      /* The maximum number of CPUs depends on the GIC version, or on how
>       * many redistributors we can fit into the memory map.
> @@ -1353,8 +1368,8 @@ static void machvirt_init(MachineState *machine)
>              object_property_set_bool(cpuobj, false, "has_el3", NULL);
>          }
>  
> -        if (vms->using_psci) {
> -            object_property_set_int(cpuobj, QEMU_PSCI_CONDUIT_HVC,
> +        if (vms->psci_conduit != QEMU_PSCI_CONDUIT_DISABLED) {
> +            object_property_set_int(cpuobj, vms->psci_conduit,
>                                      "psci-conduit", NULL);
>  
>              /* Secondary CPUs start in PSCI powered-down state */
> -- 
> 2.7.4
> 

  reply	other threads:[~2016-12-13 12:38 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-12-13 10:36 [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 01/23] target-arm: Log AArch64 exception returns Peter Maydell
2016-12-19 21:51   ` Alistair Francis
2016-12-20 15:31   ` Andrew Jones
2016-12-27 15:13     ` Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 02/23] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 03/23] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 04/23] hw/arm/virt: add 2.9 machine type Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 05/23] hw/arm/virt: Merge VirtBoardInfo and VirtMachineState Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 06/23] hw/arm/virt: Rename 'vbi' variables to 'vms' Peter Maydell
2016-12-20 15:46   ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 07/23] hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 08/23] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 09/23] hw/intc/arm_gic: " Peter Maydell
2016-12-19 21:54   ` Alistair Francis
2016-12-13 10:36 ` [Qemu-devel] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt Peter Maydell
2016-12-13 12:37   ` Edgar E. Iglesias
2016-12-13 10:36 ` [Qemu-devel] [PATCH 11/23] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 12/23] target-arm: Add ARMCPU fields for GIC CPU i/f config Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 13/23] hw/intc/gicv3: Add defines for ICH system register fields Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 14/23] hw/intc/gicv3: Add data fields for virtualization support Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 15/23] hw/intc/arm_gicv3: Add accessors for ICH_ system registers Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 16/23] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 17/23] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 18/23] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 20/23] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 21/23] hw/arm/virt: Support using SMC for PSCI Peter Maydell
2016-12-13 12:36   ` Edgar E. Iglesias [this message]
2016-12-28 13:14   ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 22/23] target-arm: Enable EL2 feature bit on A53 and A57 Peter Maydell
2016-12-13 16:11   ` Edgar E. Iglesias
2016-12-19 22:04     ` Alistair Francis
2016-12-20 13:32       ` Peter Maydell
2016-12-20 17:46         ` Alistair Francis
2016-12-28 13:14   ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2 Peter Maydell
2016-12-28 13:14   ` Andrew Jones
2017-01-17 22:15     ` Alistair Francis
2016-12-13 21:16 ` [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Andrew Jones
2016-12-14 10:18   ` Peter Maydell
2017-01-09 15:08   ` Peter Maydell
2016-12-16 21:42 ` Andrew Jones
2016-12-19 22:20 ` Alistair Francis
2017-01-09 15:57   ` Peter Maydell

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