From: Andrew Jones <drjones@redhat.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
Christoffer Dall <christoffer.dall@linaro.org>,
patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs
Date: Tue, 13 Dec 2016 22:16:06 +0100 [thread overview]
Message-ID: <20161213211606.x4cssgt4knld4m4z@hawk.localdomain> (raw)
In-Reply-To: <1481625384-15077-1-git-send-email-peter.maydell@linaro.org>
On Tue, Dec 13, 2016 at 10:36:01AM +0000, Peter Maydell wrote:
> This patchset adds support for the Virtualization extensions to QEMU's
> GICv3 emulation. This was the last missing piece that was stopping
> us from turning on the EL2 support in the CPU model, so the patchset
> also adds support for enabling it all on the virt board via the
> '-machine virtualization=on' option.
>
> The result works well enough to allow booting a KVM outer guest kernel
> and then running QEMU + an inner guest under KVM inside it. The outer
> guest KVM also passes the kvm-unit-tests GIC tests.
>
I've started some testing with this. When I boot an outer (L1) kernel
with more than one cpu allocated I get
[ 3.441908] CPU: CPUs started in inconsistent modes
[ 3.442787] ------------[ cut here ]------------
[ 3.445434] WARNING: CPU: 0 PID: 1 at arch/arm64/kernel/smp.c:418 smp_cpus_done+0x80/0xa0
...
and KVM does not init. Booting with only one cpu I see we do start in EL2
and KVM does init. I'm booting the L1 kernel through UEFI (AAVMF). Also,
my L1 guest kernel is 4.9 based, but not pure upstream. I can try a more
pure 4.9 kernel with a defconfig later.
Thanks,
drew
next prev parent reply other threads:[~2016-12-13 21:16 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-13 10:36 [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 01/23] target-arm: Log AArch64 exception returns Peter Maydell
2016-12-19 21:51 ` Alistair Francis
2016-12-20 15:31 ` Andrew Jones
2016-12-27 15:13 ` Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 02/23] hw/intc/arm_gicv3: Remove incorrect usage of fieldoffset Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 03/23] hw/intc/arm_gicv3: Don't signal Pending+Active interrupts to CPU Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 04/23] hw/arm/virt: add 2.9 machine type Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 05/23] hw/arm/virt: Merge VirtBoardInfo and VirtMachineState Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 06/23] hw/arm/virt: Rename 'vbi' variables to 'vms' Peter Maydell
2016-12-20 15:46 ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 07/23] hw/arm/virt: Don't incorrectly claim architectural timer to be edge-triggered Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 08/23] hw/intc/arm_gicv3: Add external IRQ lines for VIRQ and VFIQ Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 09/23] hw/intc/arm_gic: " Peter Maydell
2016-12-19 21:54 ` Alistair Francis
2016-12-13 10:36 ` [Qemu-devel] [PATCH 10/23] target-arm: Expose output GPIO line for VCPU maintenance interrupt Peter Maydell
2016-12-13 12:37 ` Edgar E. Iglesias
2016-12-13 10:36 ` [Qemu-devel] [PATCH 11/23] hw/arm/virt: Wire VIRQ, VFIQ, maintenance irq lines from GIC to CPU Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 12/23] target-arm: Add ARMCPU fields for GIC CPU i/f config Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 13/23] hw/intc/gicv3: Add defines for ICH system register fields Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 14/23] hw/intc/gicv3: Add data fields for virtualization support Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 15/23] hw/intc/arm_gicv3: Add accessors for ICH_ system registers Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 16/23] hw/intc/arm_gicv3: Implement ICV_ registers which are just accessors Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 17/23] hw/intc/arm_gicv3: Implement ICV_ HPPIR, DIR and RPR registers Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 18/23] hw/intc/arm_gicv3: Implement ICV_ registers EOIR and IAR Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 19/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_virt_update() Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 20/23] hw/intc/arm_gicv3: Implement EL2 traps for CPU i/f regs Peter Maydell
2016-12-13 10:36 ` [Qemu-devel] [PATCH 21/23] hw/arm/virt: Support using SMC for PSCI Peter Maydell
2016-12-13 12:36 ` Edgar E. Iglesias
2016-12-28 13:14 ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 22/23] target-arm: Enable EL2 feature bit on A53 and A57 Peter Maydell
2016-12-13 16:11 ` Edgar E. Iglesias
2016-12-19 22:04 ` Alistair Francis
2016-12-20 13:32 ` Peter Maydell
2016-12-20 17:46 ` Alistair Francis
2016-12-28 13:14 ` Andrew Jones
2016-12-13 10:36 ` [Qemu-devel] [PATCH 23/23] hw/arm/virt: Add board property to enable EL2 Peter Maydell
2016-12-28 13:14 ` Andrew Jones
2017-01-17 22:15 ` Alistair Francis
2016-12-13 21:16 ` Andrew Jones [this message]
2016-12-14 10:18 ` [Qemu-devel] [PATCH 00/23] arm: Add virtualization to GICv3, and enable EL2 on 64-bit CPUs Peter Maydell
2017-01-09 15:08 ` Peter Maydell
2016-12-16 21:42 ` Andrew Jones
2016-12-19 22:20 ` Alistair Francis
2017-01-09 15:57 ` Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20161213211606.x4cssgt4knld4m4z@hawk.localdomain \
--to=drjones@redhat.com \
--cc=christoffer.dall@linaro.org \
--cc=edgar.iglesias@gmail.com \
--cc=patches@linaro.org \
--cc=peter.maydell@linaro.org \
--cc=qemu-arm@nongnu.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).