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Date: Fri, 16 Dec 2016 16:11:24 +0300
From: "Kirill A. Shutemov" <kirill@shutemov.name>
Message-ID: <20161216131124.GG27758@node>
References: <20161215001305.146807-1-kirill.shutemov@linux.intel.com>
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Subject: Re: [Qemu-devel] [PATCH] x86: implement la57 paging mode
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To: Paolo Bonzini <pbonzini@redhat.com>
Cc: "Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>, Richard Henderson <rth@twiddle.net>, Eduardo Habkost <ehabkost@redhat.com>, qemu-devel@nongnu.org

On Fri, Dec 16, 2016 at 01:59:36PM +0100, Paolo Bonzini wrote:
> 
> 
> On 15/12/2016 01:13, Kirill A. Shutemov wrote:
> > The new paging more is extension of IA32e mode with more additional page
> > table level.
> > 
> > It brings support of 57-bit vitrual address space (128PB) and 52-bit
> > physical address space (4PB).
> > 
> > The structure of new page table level is identical to pml4.
> > 
> > The feature is enumerated with CPUID.(EAX=07H, ECX=0):ECX[bit 16].
> > 
> > CR4.LA57[bit 12] need to be set when pageing enables to activate 5-level
> > paging mode.
> > 
> > Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
> 
> Looks good, thanks!  The target-i386/translate.c bits are not necessary,
> but I guess they can also be removed on commit.
> 
> Any chance you could also implement the MPX bits?

I don't have time for this right now. Maybe later.

-- 
 Kirill A. Shutemov