From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38441) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cQHhn-00035s-2o for qemu-devel@nongnu.org; Sun, 08 Jan 2017 12:56:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cQHhl-0003vL-V2 for qemu-devel@nongnu.org; Sun, 08 Jan 2017 12:56:31 -0500 Received: from mail-pg0-x244.google.com ([2607:f8b0:400e:c05::244]:35864) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cQHhl-0003vA-PC for qemu-devel@nongnu.org; Sun, 08 Jan 2017 12:56:29 -0500 Received: by mail-pg0-x244.google.com with SMTP id 75so11154944pgf.3 for ; Sun, 08 Jan 2017 09:56:29 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Sun, 8 Jan 2017 09:56:18 -0800 Message-Id: <20170108175620.6605-10-rth@twiddle.net> In-Reply-To: <20170108175620.6605-1-rth@twiddle.net> References: <20170108175620.6605-1-rth@twiddle.net> Subject: [Qemu-devel] [PULL 09/11] tcg-mips: Adjust calling conventions for mips64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, Jin Guojie From: Jin Guojie Tested-by: Aurelien Jarno Tested-by: James Hogan Tested-by: YunQiang Su Signed-off-by: Richard Henderson Signed-off-by: Jin Guojie Message-Id: <1483592275-4496-10-git-send-email-jinguojie@loongson.cn> --- tcg/mips/tcg-target.h | 19 +++++++++++++++---- tcg/mips/tcg-target.inc.c | 21 +++++++++++++++------ 2 files changed, 30 insertions(+), 10 deletions(-) diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 4b7d3ae..d352c97 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -27,7 +27,14 @@ #ifndef MIPS_TCG_TARGET_H #define MIPS_TCG_TARGET_H -#define TCG_TARGET_REG_BITS 32 +#if _MIPS_SIM == _ABIO32 +# define TCG_TARGET_REG_BITS 32 +#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 +# define TCG_TARGET_REG_BITS 64 +#else +# error "Unknown ABI" +#endif + #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 #define TCG_TARGET_NB_REGS 32 @@ -71,9 +78,13 @@ typedef enum { } TCGReg; /* used for function call generation */ -#define TCG_TARGET_STACK_ALIGN 8 -#define TCG_TARGET_CALL_STACK_OFFSET 16 -#define TCG_TARGET_CALL_ALIGN_ARGS 1 +#define TCG_TARGET_STACK_ALIGN 16 +#if _MIPS_SIM == _ABIO32 +# define TCG_TARGET_CALL_STACK_OFFSET 16 +#else +# define TCG_TARGET_CALL_STACK_OFFSET 0 +#endif +#define TCG_TARGET_CALL_ALIGN_ARGS 1 /* MOVN/MOVZ instructions detection */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c index b7e2586..7282a4a 100644 --- a/tcg/mips/tcg-target.inc.c +++ b/tcg/mips/tcg-target.inc.c @@ -91,10 +91,6 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_S8, /* Call clobbered registers. */ - TCG_REG_T0, - TCG_REG_T1, - TCG_REG_T2, - TCG_REG_T3, TCG_REG_T4, TCG_REG_T5, TCG_REG_T6, @@ -105,17 +101,27 @@ static const int tcg_target_reg_alloc_order[] = { TCG_REG_V0, /* Argument registers, opposite order of allocation. */ + TCG_REG_T3, + TCG_REG_T2, + TCG_REG_T1, + TCG_REG_T0, TCG_REG_A3, TCG_REG_A2, TCG_REG_A1, TCG_REG_A0, }; -static const TCGReg tcg_target_call_iarg_regs[4] = { +static const TCGReg tcg_target_call_iarg_regs[] = { TCG_REG_A0, TCG_REG_A1, TCG_REG_A2, - TCG_REG_A3 + TCG_REG_A3, +#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, +#endif }; static const TCGReg tcg_target_call_oarg_regs[2] = { @@ -2427,6 +2433,9 @@ static void tcg_target_init(TCGContext *s) { tcg_target_detect_isa(); tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I32], 0xffffffff); + if (TCG_TARGET_REG_BITS == 64) { + tcg_regset_set(tcg_target_available_regs[TCG_TYPE_I64], 0xffffffff); + } tcg_regset_set(tcg_target_call_clobber_regs, (1 << TCG_REG_V0) | (1 << TCG_REG_V1) | -- 2.9.3