From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, Jin Guojie <jinguojie@loongson.cn>
Subject: [Qemu-devel] [PULL 05/11] tcg-mips: Adjust move functions for mips64
Date: Sun, 8 Jan 2017 09:56:14 -0800 [thread overview]
Message-ID: <20170108175620.6605-6-rth@twiddle.net> (raw)
In-Reply-To: <20170108175620.6605-1-rth@twiddle.net>
From: Jin Guojie <jinguojie@loongson.cn>
tcg_out_mov: using OPC_OR as most mips assemblers do;
tcg_out_movi: extended to 64-bit immediate.
Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Tested-by: James Hogan <james.hogan@imgtec.com>
Tested-by: YunQiang Su <wzssyqa@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Jin Guojie <jinguojie@loongson.cn>
Message-Id: <1483592275-4496-6-git-send-email-jinguojie@loongson.cn>
---
tcg/mips/tcg-target.inc.c | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index ec139cd..18368f0 100644
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.inc.c
@@ -544,23 +544,39 @@ static inline void tcg_out_mov(TCGContext *s, TCGType type,
{
/* Simple reg-reg move, optimising out the 'do nothing' case */
if (ret != arg) {
- tcg_out_opc_reg(s, OPC_ADDU, ret, arg, TCG_REG_ZERO);
+ tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO);
}
}
-static inline void tcg_out_movi(TCGContext *s, TCGType type,
- TCGReg reg, tcg_target_long arg)
+static void tcg_out_movi(TCGContext *s, TCGType type,
+ TCGReg ret, tcg_target_long arg)
{
+ if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) {
+ arg = (int32_t)arg;
+ }
if (arg == (int16_t)arg) {
- tcg_out_opc_imm(s, OPC_ADDIU, reg, TCG_REG_ZERO, arg);
- } else if (arg == (uint16_t)arg) {
- tcg_out_opc_imm(s, OPC_ORI, reg, TCG_REG_ZERO, arg);
+ tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg);
+ return;
+ }
+ if (arg == (uint16_t)arg) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg);
+ return;
+ }
+ if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) {
+ tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16);
} else {
- tcg_out_opc_imm(s, OPC_LUI, reg, TCG_REG_ZERO, arg >> 16);
- if (arg & 0xffff) {
- tcg_out_opc_imm(s, OPC_ORI, reg, reg, arg & 0xffff);
+ tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1);
+ if (arg & 0xffff0000ull) {
+ tcg_out_dsll(s, ret, ret, 16);
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16);
+ tcg_out_dsll(s, ret, ret, 16);
+ } else {
+ tcg_out_dsll(s, ret, ret, 32);
}
}
+ if (arg & 0xffff) {
+ tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff);
+ }
}
static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg)
--
2.9.3
next prev parent reply other threads:[~2017-01-08 17:56 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-08 17:56 [Qemu-devel] [PULL 00/11] tcg host mips64 support Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 01/11] tcg-mips: Move bswap code to a subroutine Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 02/11] tcg-mips: Add mips64 opcodes Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 03/11] tcg-mips: Support 64-bit opcodes Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 04/11] tcg-mips: Add bswap32u and bswap64 Richard Henderson
2017-01-08 17:56 ` Richard Henderson [this message]
2017-01-08 17:56 ` [Qemu-devel] [PULL 06/11] tcg-mips: Adjust load/store functions for mips64 Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 07/11] tcg-mips: Adjust prologue " Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 08/11] tcg-mips: Add tcg unwind info Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 09/11] tcg-mips: Adjust calling conventions for mips64 Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 10/11] tcg-mips: Adjust qemu_ld/st " Richard Henderson
2017-01-08 17:56 ` [Qemu-devel] [PULL 11/11] translate-all: Avoid -Werror=switch-bool Richard Henderson
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