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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 65/65] tcg/i386: Handle ctpop opcode
Date: Tue, 10 Jan 2017 18:18:20 -0800	[thread overview]
Message-ID: <20170111021820.24416-66-rth@twiddle.net> (raw)
In-Reply-To: <20170111021820.24416-1-rth@twiddle.net>

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/i386/tcg-target.h     |  5 +++--
 tcg/i386/tcg-target.inc.c | 12 +++++++++++-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h
index b8f73f5..21d96ec 100644
--- a/tcg/i386/tcg-target.h
+++ b/tcg/i386/tcg-target.h
@@ -76,6 +76,7 @@ typedef enum {
 #endif
 
 extern bool have_bmi1;
+extern bool have_popcnt;
 
 /* optional instructions */
 #define TCG_TARGET_HAS_div2_i32         1
@@ -95,7 +96,7 @@ extern bool have_bmi1;
 #define TCG_TARGET_HAS_nor_i32          0
 #define TCG_TARGET_HAS_clz_i32          1
 #define TCG_TARGET_HAS_ctz_i32          1
-#define TCG_TARGET_HAS_ctpop_i32        0
+#define TCG_TARGET_HAS_ctpop_i32        have_popcnt
 #define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_extract_i32      1
 #define TCG_TARGET_HAS_sextract_i32     1
@@ -130,7 +131,7 @@ extern bool have_bmi1;
 #define TCG_TARGET_HAS_nor_i64          0
 #define TCG_TARGET_HAS_clz_i64          1
 #define TCG_TARGET_HAS_ctz_i64          1
-#define TCG_TARGET_HAS_ctpop_i64        0
+#define TCG_TARGET_HAS_ctpop_i64        have_popcnt
 #define TCG_TARGET_HAS_deposit_i64      1
 #define TCG_TARGET_HAS_extract_i64      1
 #define TCG_TARGET_HAS_sextract_i64     0
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 3650340..01177a9 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -130,9 +130,10 @@ static bool have_movbe;
 # define have_movbe 0
 #endif
 
-/* We need this symbol in tcg-target.h, and we can't properly conditionalize
+/* We need these symbols in tcg-target.h, and we can't properly conditionalize
    it there.  Therefore we always define the variable.  */
 bool have_bmi1;
+bool have_popcnt;
 
 #if defined(CONFIG_CPUID_H) && defined(bit_BMI2)
 static bool have_bmi2;
@@ -337,6 +338,7 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
 #define OPC_MOVZBL	(0xb6 | P_EXT)
 #define OPC_MOVZWL	(0xb7 | P_EXT)
 #define OPC_POP_r32	(0x58)
+#define OPC_POPCNT      (0xb8 | P_EXT | P_SIMDF3)
 #define OPC_PUSH_r32	(0x50)
 #define OPC_PUSH_Iv	(0x68)
 #define OPC_PUSH_Ib	(0x6a)
@@ -2083,6 +2085,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
     OP_32_64(clz):
         tcg_out_clz(s, rexw, args[0], args[1], args[2], const_args[2]);
         break;
+    OP_32_64(ctpop):
+        tcg_out_modrm(s, OPC_POPCNT + rexw, a0, a1);
+        break;
 
     case INDEX_op_brcond_i32:
         tcg_out_brcond32(s, a2, a0, a1, const_args[1], arg_label(args[3]), 0);
@@ -2398,6 +2403,8 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
     case INDEX_op_extract_i32:
     case INDEX_op_extract_i64:
     case INDEX_op_sextract_i32:
+    case INDEX_op_ctpop_i32:
+    case INDEX_op_ctpop_i64:
         return &r_r;
 
     case INDEX_op_deposit_i32:
@@ -2602,6 +2609,9 @@ static void tcg_target_init(TCGContext *s)
            need to probe for it.  */
         have_movbe = (c & bit_MOVBE) != 0;
 #endif
+#ifdef bit_POPCNT
+        have_popcnt = (c & bit_POPCNT) != 0;
+#endif
     }
 
     if (max >= 7) {
-- 
2.9.3

  parent reply	other threads:[~2017-01-11  2:19 UTC|newest]

Thread overview: 73+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-11  2:17 [Qemu-devel] [PULL 00/65] tcg 2.9 patch queue Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 01/65] tcg: Add field extraction primitives Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 02/65] tcg: Minor adjustments to deposit expanders Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 03/65] tcg: Add deposit_z expander Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 04/65] tcg/aarch64: Implement field extraction opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 05/65] tcg/arm: Move isa detection to tcg-target.h Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 06/65] tcg/arm: Implement field extraction opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 07/65] tcg/i386: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 08/65] tcg/mips: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 09/65] tcg/ppc: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 10/65] tcg/s390: Expose host facilities to tcg-target.h Richard Henderson
2017-01-13  9:18   ` Christian Borntraeger
2017-01-16  8:28     ` Christian Borntraeger
2017-01-11  2:17 ` [Qemu-devel] [PULL 11/65] tcg/s390: Implement field extraction opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 12/65] tcg/s390: Support deposit into zero Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 13/65] target-alpha: Use deposit and extract ops Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 14/65] target-arm: Use new " Richard Henderson
2017-01-14 19:41   ` Laszlo Ersek
2017-01-14 20:13     ` Richard Henderson
2017-01-16 23:05       ` Laszlo Ersek
2017-01-11  2:17 ` [Qemu-devel] [PULL 15/65] target-i386: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 16/65] target-mips: Use the new extract op Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 17/65] target-ppc: Use the new deposit and extract ops Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 18/65] target-s390x: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 19/65] tcg/optimize: Fold movcond 0/1 into setcond Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 20/65] tcg: Add markup for output requires new register Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 21/65] tcg: Transition flat op_defs array to a target callback Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 22/65] tcg: Pass the opcode width to target_parse_constraint Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 23/65] tcg: Allow an operand to be matching or a constant Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 24/65] tcg: Add clz and ctz opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 25/65] disas/i386.c: Handle tzcnt Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 26/65] disas/ppc: Handle popcnt and cnttz Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 27/65] target-alpha: Use the ctz and clz opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 28/65] target-cris: Use clz opcode Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 29/65] target-microblaze: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 30/65] target-mips: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 31/65] target-openrisc: Use clz and ctz opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 32/65] target-ppc: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 33/65] target-s390x: Use clz opcode Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 34/65] target-tilegx: Use clz and ctz opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 35/65] target-tricore: Use clz opcode Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 36/65] target-unicore32: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 37/65] target-xtensa: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 38/65] target-arm: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 39/65] target-i386: Use clz and ctz opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 40/65] tcg/ppc: Handle ctz and clz opcodes Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 41/65] tcg/aarch64: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 42/65] tcg/arm: " Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 43/65] tcg/mips: Handle clz opcode Richard Henderson
2017-01-11  2:17 ` [Qemu-devel] [PULL 44/65] tcg/s390: " Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 45/65] tcg/i386: Fuly convert tcg_target_op_def Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 46/65] tcg/i386: Hoist common arguments in tcg_out_op Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 47/65] tcg/i386: Allow bmi2 shiftx to have non-matching operands Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 48/65] tcg/i386: Handle ctz and clz opcodes Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 49/65] tcg/i386: Rely on undefined/undocumented behaviour of BSF/BSR Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 50/65] tcg: Add helpers for clrsb Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 51/65] target-arm: Use clrsb helper Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 52/65] target-tricore: " Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 53/65] target-xtensa: " Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 54/65] tcg: Add opcode for ctpop Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 55/65] target-alpha: Use ctpop helper Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 56/65] target-ppc: " Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 57/65] target-s390x: Avoid a loop for popcnt Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 58/65] target-sparc: Use ctpop helper Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 59/65] target-tilegx: " Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 60/65] target-i386: " Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 61/65] qemu/host-utils.h: Reduce the operation count in the fallback ctpop Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 62/65] tests: New test-bitcnt Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 63/65] tcg: Use ctpop to generate ctz if needed Richard Henderson
2017-01-11  2:18 ` [Qemu-devel] [PULL 64/65] tcg/ppc: Handle ctpop opcode Richard Henderson
2017-01-11  2:18 ` Richard Henderson [this message]
2017-01-11  3:39 ` [Qemu-devel] [PULL 00/65] tcg 2.9 patch queue no-reply
2017-01-12 15:57 ` Peter Maydell

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