From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47103) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRUkH-0003GW-48 for qemu-devel@nongnu.org; Wed, 11 Jan 2017 21:04:08 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cRUkE-0006pa-5N for qemu-devel@nongnu.org; Wed, 11 Jan 2017 21:04:05 -0500 From: David Gibson Date: Thu, 12 Jan 2017 13:03:18 +1100 Message-Id: <20170112020327.24882-59-david@gibson.dropbear.id.au> In-Reply-To: <20170112020327.24882-1-david@gibson.dropbear.id.au> References: <20170112020327.24882-1-david@gibson.dropbear.id.au> Subject: [Qemu-devel] [PULL 58/67] target-ppc: Add xsxsigdp instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: peter.maydell@linaro.org Cc: agraf@suse.de, qemu-ppc@nongnu.org, qemu-devel@nongnu.org, thuth@redhat.com, lvivier@redhat.com, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com, Nikunj A Dadhania , David Gibson From: Nikunj A Dadhania xsxsigdp: VSX Scalar Extract Significand Dual Precision Signed-off-by: Nikunj A Dadhania Signed-off-by: David Gibson --- target/ppc/translate/vsx-impl.inc.c | 29 +++++++++++++++++++++++++++++ target/ppc/translate/vsx-ops.inc.c | 1 + 2 files changed, 30 insertions(+) diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index 228e2a5..c6f2208 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1239,6 +1239,35 @@ static void gen_xsxexpqp(DisasContext *ctx) tcg_gen_andi_i64(xth, xth, 0x7FFF); tcg_gen_movi_i64(xtl, 0); } + +static void gen_xsxsigdp(DisasContext *ctx) +{ + TCGv rt = cpu_gpr[rD(ctx->opcode)]; + TCGv_i64 t0, zr, nan, exp; + + if (unlikely(!ctx->vsx_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VSXU); + return; + } + exp = tcg_temp_new_i64(); + t0 = tcg_temp_new_i64(); + zr = tcg_const_i64(0); + nan = tcg_const_i64(2047); + + tcg_gen_shri_i64(exp, cpu_vsrh(xB(ctx->opcode)), 52); + tcg_gen_andi_i64(exp, exp, 0x7FF); + tcg_gen_movi_i64(t0, 0x0010000000000000); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, zr, zr, t0); + tcg_gen_movcond_i64(TCG_COND_EQ, t0, exp, nan, zr, t0); + tcg_gen_andi_i64(rt, cpu_vsrh(xB(ctx->opcode)), 0x000FFFFFFFFFFFFF); + tcg_gen_or_i64(rt, rt, t0); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(exp); + tcg_temp_free_i64(zr); + tcg_temp_free_i64(nan); +} + #endif #undef GEN_XX2FORM diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.inc.c index 87f1852..1fd5285 100644 --- a/target/ppc/translate/vsx-ops.inc.c +++ b/target/ppc/translate/vsx-ops.inc.c @@ -116,6 +116,7 @@ GEN_VSX_XFORM_300(xscpsgnqp, 0x04, 0x03, 0x00000001), #ifdef TARGET_PPC64 GEN_XX2FORM_EO(xsxexpdp, 0x16, 0x15, 0x00, PPC2_ISA300), GEN_VSX_XFORM_300_EO(xsxexpqp, 0x04, 0x19, 0x02, 0x00000001), +GEN_XX2FORM_EO(xsxsigdp, 0x16, 0x15, 0x01, PPC2_ISA300), #endif GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX), -- 2.9.3