* [Qemu-devel] [PATCH v5 1/7] host-utils: Move 128-bit guard macro to .c file
2017-01-10 2:10 [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
@ 2017-01-10 2:10 ` Jose Ricardo Ziviani
2017-01-10 14:26 ` Eric Blake
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests Jose Ricardo Ziviani
` (6 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-10 2:10 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata, eblake
It is not possible to implement functions in host-utils.c for
architectures with quadwords because the guard is implemented in the
Makefile. This patch move the guard out of the Makefile to the
implementation file.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
util/Makefile.objs | 2 +-
util/host-utils.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/util/Makefile.objs b/util/Makefile.objs
index ad0f9c7..39ae26e 100644
--- a/util/Makefile.objs
+++ b/util/Makefile.objs
@@ -11,7 +11,7 @@ util-obj-$(CONFIG_POSIX) += memfd.o
util-obj-$(CONFIG_WIN32) += oslib-win32.o
util-obj-$(CONFIG_WIN32) += qemu-thread-win32.o
util-obj-y += envlist.o path.o module.o
-util-obj-$(call lnot,$(CONFIG_INT128)) += host-utils.o
+util-obj-y += host-utils.o
util-obj-y += bitmap.o bitops.o hbitmap.o
util-obj-y += fifo8.o
util-obj-y += acl.o
diff --git a/util/host-utils.c b/util/host-utils.c
index b166e57..3495262 100644
--- a/util/host-utils.c
+++ b/util/host-utils.c
@@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qemu/host-utils.h"
+#ifndef CONFIG_INT128
/* Long integer helpers */
static inline void mul64(uint64_t *plow, uint64_t *phigh,
uint64_t a, uint64_t b)
@@ -158,4 +159,5 @@ int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
return overflow;
}
+#endif
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH v5 1/7] host-utils: Move 128-bit guard macro to .c file
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 1/7] host-utils: Move 128-bit guard macro to .c file Jose Ricardo Ziviani
@ 2017-01-10 14:26 ` Eric Blake
0 siblings, 0 replies; 13+ messages in thread
From: Eric Blake @ 2017-01-10 14:26 UTC (permalink / raw)
To: Jose Ricardo Ziviani, qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata
[-- Attachment #1: Type: text/plain, Size: 651 bytes --]
On 01/09/2017 08:10 PM, Jose Ricardo Ziviani wrote:
> It is not possible to implement functions in host-utils.c for
> architectures with quadwords because the guard is implemented in the
> Makefile. This patch move the guard out of the Makefile to the
s/move/moves/
> implementation file.
>
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
> util/Makefile.objs | 2 +-
> util/host-utils.c | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
>
Reviewed-by: Eric Blake <eblake@redhat.com>
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
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^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests
2017-01-10 2:10 [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 1/7] host-utils: Move 128-bit guard macro to .c file Jose Ricardo Ziviani
@ 2017-01-10 2:10 ` Jose Ricardo Ziviani
2017-01-10 14:34 ` Eric Blake
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 3/7] ppc: Implement bcds. instruction Jose Ricardo Ziviani
` (5 subsequent siblings)
7 siblings, 1 reply; 13+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-10 2:10 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata, eblake
Implements 128-bit left shift and right shift as well as their
testcases. By design, shift silently mods by 128, so the caller is
responsible to assert the shift range if necessary.
Left shift sets the overflow flag if any non-zero digit is shifted out.
Examples:
ulshift(&low, &high, 250, &overflow);
equivalent: n << 122
urshift(&low, &high, -2);
equivalent: n << 126
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
include/qemu/host-utils.h | 27 +++++++++
tests/Makefile.include | 5 +-
tests/test-shift128.c | 139 ++++++++++++++++++++++++++++++++++++++++++++++
util/host-utils.c | 64 +++++++++++++++++++++
4 files changed, 234 insertions(+), 1 deletion(-)
create mode 100644 tests/test-shift128.c
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 46187bb..89c3dc7 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -516,4 +516,31 @@ static inline uint64_t pow2ceil(uint64_t value)
return 1ULL << (64 - nlz);
}
+/**
+ * urshift - 128-bit Unsigned Right Shift.
+ * @plow: in/out - lower 64-bit integer.
+ * @phigh: in/out - higher 64-bit integer.
+ * @shift: in - bytes to shift, between 0 and 127.
+ *
+ * Result is zero-extended and stored in plow/phigh, which are
+ * input/output variables. Shift values outside the range will
+ * be mod to 128. In other words, the caller is responsible to
+ * verify/assert both the shift range and plow/phigh pointers.
+ */
+void urshift(uint64_t *plow, uint64_t *phigh, int32_t shift);
+
+/**
+ * ulshift - 128-bit Unsigned Left Shift.
+ * @plow: in/out - lower 64-bit integer.
+ * @phigh: in/out - higher 64-bit integer.
+ * @shift: in - bytes to shift, between 0 and 127.
+ * @overflow: out - true if any 1-bit is shifted out.
+ *
+ * Result is zero-extended and stored in plow/phigh, which are
+ * input/output variables. Shift values outside the range will
+ * be mod to 128. In other words, the caller is responsible to
+ * verify/assert both the shift range and plow/phigh pointers.
+ */
+void ulshift(uint64_t *plow, uint64_t *phigh, int32_t shift, bool *overflow);
+
#endif
diff --git a/tests/Makefile.include b/tests/Makefile.include
index 0bb939d..1981a32 100644
--- a/tests/Makefile.include
+++ b/tests/Makefile.include
@@ -65,6 +65,8 @@ check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF)
endif
check-unit-y += tests/test-cutils$(EXESUF)
gcov-files-test-cutils-y += util/cutils.c
+check-unit-y += tests/test-shift128$(EXESUF)
+gcov-files-test-shift128-y = util/host-utils.c
check-unit-y += tests/test-mul64$(EXESUF)
gcov-files-test-mul64-y = util/host-utils.c
check-unit-y += tests/test-int128$(EXESUF)
@@ -466,7 +468,7 @@ test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \
tests/test-x86-cpuid.o tests/test-mul64.o tests/test-int128.o \
tests/test-opts-visitor.o tests/test-qmp-event.o \
tests/rcutorture.o tests/test-rcu-list.o \
- tests/test-qdist.o \
+ tests/test-qdist.o tests/test-shift128.o \
tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \
tests/atomic_add-bench.o
@@ -574,6 +576,7 @@ tests/test-qmp-commands$(EXESUF): tests/test-qmp-commands.o tests/test-qmp-marsh
tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(test-qapi-obj-y)
tests/test-opts-visitor$(EXESUF): tests/test-opts-visitor.o $(test-qapi-obj-y)
+tests/test-shift128$(EXESUF): tests/test-shift128.o $(test-util-obj-y)
tests/test-mul64$(EXESUF): tests/test-mul64.o $(test-util-obj-y)
tests/test-bitops$(EXESUF): tests/test-bitops.o $(test-util-obj-y)
tests/test-crypto-hash$(EXESUF): tests/test-crypto-hash.o $(test-crypto-obj-y)
diff --git a/tests/test-shift128.c b/tests/test-shift128.c
new file mode 100644
index 0000000..f3ff736
--- /dev/null
+++ b/tests/test-shift128.c
@@ -0,0 +1,139 @@
+/*
+ * Test unsigned left and right shift
+ *
+ * This work is licensed under the terms of the GNU LGPL, version 2 or later.
+ * See the COPYING.LIB file in the top-level directory.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/host-utils.h"
+
+typedef struct {
+ uint64_t low;
+ uint64_t high;
+ uint64_t rlow;
+ uint64_t rhigh;
+ int32_t shift;
+ bool overflow;
+} test_data;
+
+static const test_data test_ltable[] = {
+ { 0x4C7ULL, 0x0ULL, 0x00000000000004C7ULL,
+ 0x0000000000000000ULL, 0, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000002ULL,
+ 0x0000000000000000ULL, 1, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000004ULL,
+ 0x0000000000000000ULL, 2, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000010ULL,
+ 0x0000000000000000ULL, 4, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000100ULL,
+ 0x0000000000000000ULL, 8, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000010000ULL,
+ 0x0000000000000000ULL, 16, false },
+ { 0x001ULL, 0x0ULL, 0x0000000080000000ULL,
+ 0x0000000000000000ULL, 31, false },
+ { 0x001ULL, 0x0ULL, 0x0000200000000000ULL,
+ 0x0000000000000000ULL, 45, false },
+ { 0x001ULL, 0x0ULL, 0x1000000000000000ULL,
+ 0x0000000000000000ULL, 60, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x0000000000000001ULL, 64, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x0000000000010000ULL, 80, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x8000000000000000ULL, 127, false },
+ { 0x000ULL, 0x1ULL, 0x0000000000000000ULL,
+ 0x0000000000000000ULL, 64, true },
+ { 0x008ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x0000000000000008ULL, 64, false },
+ { 0x008ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x8000000000000000ULL, 124, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x4000000000000000ULL, 126, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x8000000000000000ULL, 127, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000001ULL,
+ 0x0000000000000000ULL, 128, false },
+ { 0x000ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x0000000000000000ULL, 200, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x0000000000000100ULL, 200, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x8000000000000000ULL, -1, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x8000000000000000ULL, INT32_MAX, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x4000000000000000ULL, -2, false },
+ { 0x001ULL, 0x0ULL, 0x0000000000000000ULL,
+ 0x4000000000000000ULL, INT32_MAX - 1, false },
+ { 0x8888888888888888ULL, 0x9999999999999999ULL,
+ 0x8000000000000000ULL, 0x9888888888888888ULL, 60, true },
+ { 0x8888888888888888ULL, 0x9999999999999999ULL,
+ 0x0000000000000000ULL, 0x8888888888888888ULL, 64, true },
+};
+
+static const test_data test_rtable[] = {
+ { 0x00000000000004C7ULL, 0x0ULL, 0x00000000000004C7ULL, 0x0ULL, 0, false },
+ { 0x0800000000000000ULL, 0x0ULL, 0x0400000000000000ULL, 0x0ULL, 1, false },
+ { 0x0800000000000000ULL, 0x0ULL, 0x0200000000000000ULL, 0x0ULL, 2, false },
+ { 0x0800000000000000ULL, 0x0ULL, 0x0008000000000000ULL, 0x0ULL, 8, false },
+ { 0x0800000000000000ULL, 0x0ULL, 0x0000080000000000ULL, 0x0ULL, 16, false },
+ { 0x0800000000000000ULL, 0x0ULL, 0x0000000008000000ULL, 0x0ULL, 32, false },
+ { 0x8000000000000000ULL, 0x0ULL, 0x0000000000000001ULL, 0x0ULL, 63, false },
+ { 0x8000000000000000ULL, 0x0ULL, 0x0000000000000000ULL, 0x0ULL, 64, false },
+ { 0x0000000000000000ULL, 0x8000000000000000ULL,
+ 0x0000000000000000ULL, 0x8000000000000000ULL, 128, false },
+ { 0x0000000000000000ULL, 0x8000000000000000ULL,
+ 0x0080000000000000ULL, 0x0000000000000000ULL, 200, false },
+ { 0x0000000000000000ULL, 0x0000000000000000ULL,
+ 0x0000000000000000ULL, 0x0000000000000000ULL, 200, false },
+ { 0x0000000000000000ULL, 0x8000000000000000ULL,
+ 0x0000000000000000ULL, 0x0000000000000080ULL, -200, false },
+ { 0x8000000000000000ULL, 0x8000000000000000ULL,
+ 0x0000000080000000ULL, 0x0000000080000000ULL, 32, false },
+ { 0x0800000000000000ULL, 0x0800000000000000ULL,
+ 0x0800000000000000ULL, 0x0000000000000000ULL, 64, false },
+ { 0x0800000000000000ULL, 0x0800000000000000ULL,
+ 0x0008000000000000ULL, 0x0000000000000000ULL, 72, false },
+ { 0x8000000000000000ULL, 0x8000000000000000ULL,
+ 0x0000000000000001ULL, 0x0000000000000000ULL, 127, false },
+ { 0x0000000000000000ULL, 0x8000000000000000ULL,
+ 0x0000000000000001ULL, 0x0000000000000000ULL, -1, false },
+ { 0x0000000000000000ULL, 0x8000000000000000ULL,
+ 0x0000000000000002ULL, 0x0000000000000000ULL, -2, false },
+};
+
+static void test_lshift(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(test_ltable); ++i) {
+ bool overflow = false;
+ test_data tmp = test_ltable[i];
+ ulshift(&tmp.low, &tmp.high, tmp.shift, &overflow);
+ g_assert_cmpuint(tmp.low, ==, tmp.rlow);
+ g_assert_cmpuint(tmp.high, ==, tmp.rhigh);
+ g_assert_cmpuint(tmp.overflow, ==, overflow);
+ }
+}
+
+static void test_rshift(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(test_rtable); ++i) {
+ test_data tmp = test_rtable[i];
+ urshift(&tmp.low, &tmp.high, tmp.shift);
+ g_assert_cmpuint(tmp.low, ==, tmp.rlow);
+ g_assert_cmpuint(tmp.high, ==, tmp.rhigh);
+ }
+}
+
+int main(int argc, char **argv)
+{
+ g_test_init(&argc, &argv, NULL);
+ g_test_add_func("/host-utils/test_lshift", test_lshift);
+ g_test_add_func("/host-utils/test_rshift", test_rshift);
+ return g_test_run();
+}
diff --git a/util/host-utils.c b/util/host-utils.c
index 3495262..7b93220 100644
--- a/util/host-utils.c
+++ b/util/host-utils.c
@@ -161,3 +161,67 @@ int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
}
#endif
+/**
+ * urshift - 128-bit Unsigned Right Shift.
+ * @plow: in/out - lower 64-bit integer.
+ * @phigh: in/out - higher 64-bit integer.
+ * @shift: in - bytes to shift, between 0 and 127.
+ *
+ * Result is zero-extended and stored in plow/phigh, which are
+ * input/output variables. Shift values outside the range will
+ * be mod to 128. In other words, the caller is responsible to
+ * verify/assert both the shift range and plow/phigh pointers.
+ */
+void urshift(uint64_t *plow, uint64_t *phigh, int32_t shift)
+{
+ shift &= 127;
+ if (shift == 0) {
+ return;
+ }
+
+ uint64_t h = *phigh >> (shift & 63);
+ if (shift >= 64) {
+ *plow = h;
+ *phigh = 0;
+ } else {
+ *plow = (*plow >> (shift & 63)) | (*phigh << (64 - (shift & 63)));
+ *phigh = h;
+ }
+}
+
+/**
+ * ulshift - 128-bit Unsigned Left Shift.
+ * @plow: in/out - lower 64-bit integer.
+ * @phigh: in/out - higher 64-bit integer.
+ * @shift: in - bytes to shift, between 0 and 127.
+ * @overflow: out - true if any 1-bit is shifted out.
+ *
+ * Result is zero-extended and stored in plow/phigh, which are
+ * input/output variables. Shift values outside the range will
+ * be mod to 128. In other words, the caller is responsible to
+ * verify/assert both the shift range and plow/phigh pointers.
+ */
+void ulshift(uint64_t *plow, uint64_t *phigh, int32_t shift, bool *overflow)
+{
+ uint64_t low = *plow;
+ uint64_t high = *phigh;
+
+ shift &= 127;
+ if (shift == 0) {
+ return;
+ }
+
+ /* check if any bit will be shifted out */
+ urshift(&low, &high, 128 - shift);
+ if (low | high) {
+ *overflow = true;
+ }
+
+ if (shift >= 64) {
+ *phigh = *plow << (shift & 63);
+ *plow = 0;
+ } else {
+ *phigh = (*plow >> (64 - (shift & 63))) | (*phigh << (shift & 63));
+ *plow = *plow << shift;
+ }
+}
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests Jose Ricardo Ziviani
@ 2017-01-10 14:34 ` Eric Blake
2017-01-12 2:52 ` David Gibson
0 siblings, 1 reply; 13+ messages in thread
From: Eric Blake @ 2017-01-10 14:34 UTC (permalink / raw)
To: Jose Ricardo Ziviani, qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata
[-- Attachment #1: Type: text/plain, Size: 2652 bytes --]
On 01/09/2017 08:10 PM, Jose Ricardo Ziviani wrote:
> Implements 128-bit left shift and right shift as well as their
> testcases. By design, shift silently mods by 128, so the caller is
> responsible to assert the shift range if necessary.
>
> Left shift sets the overflow flag if any non-zero digit is shifted out.
>
> Examples:
> ulshift(&low, &high, 250, &overflow);
> equivalent: n << 122
>
> urshift(&low, &high, -2);
> equivalent: n << 126
>
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
> +typedef struct {
> + uint64_t low;
> + uint64_t high;
> + uint64_t rlow;
> + uint64_t rhigh;
> + int32_t shift;
> + bool overflow;
> +} test_data;
> +
> +static const test_data test_ltable[] = {
> + { 0x4C7ULL, 0x0ULL, 0x00000000000004C7ULL,
> + 0x0000000000000000ULL, 0, false },
I might have laid it out as:
{ 0x00000000000004c7ULL, 0x0000000000000000ULL,
0x00000000000004c7ULL, 0x0000000000000000ULL,
0, false }
to make the pre- and post-shift values line up better. It's not fatal
to the patch, so it's up to the maintainer if they want a v6 to improve
the alignment.
> + { 0x8888888888888888ULL, 0x9999999999999999ULL,
> + 0x8000000000000000ULL, 0x9888888888888888ULL, 60, true },
> + { 0x8888888888888888ULL, 0x9999999999999999ULL,
> + 0x0000000000000000ULL, 0x8888888888888888ULL, 64, true },
These two are the most legible.
> +};
> +
> +static const test_data test_rtable[] = {
> +++ b/util/host-utils.c
> @@ -161,3 +161,67 @@ int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
> }
> #endif
>
> +/**
> + * urshift - 128-bit Unsigned Right Shift.
> + * @plow: in/out - lower 64-bit integer.
> + * @phigh: in/out - higher 64-bit integer.
> + * @shift: in - bytes to shift, between 0 and 127.
> + *
> + * Result is zero-extended and stored in plow/phigh, which are
> + * input/output variables. Shift values outside the range will
> + * be mod to 128. In other words, the caller is responsible to
> + * verify/assert both the shift range and plow/phigh pointers.
> + */
Duplicating docs in the .h and .c doesn't hurt, but risks one getting
out of date; we have other spots that put the docs in the .h (where
callers will look up what's available) or the .c (where the
implementation is there to check against the docs). I don't have any
strong preference on how to do it, though, so I don't mind leaving it as is.
Reviewed-by: Eric Blake <eblake@redhat.com>
--
Eric Blake eblake redhat com +1-919-301-3266
Libvirt virtualization library http://libvirt.org
[-- Attachment #2: OpenPGP digital signature --]
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^ permalink raw reply [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests
2017-01-10 14:34 ` Eric Blake
@ 2017-01-12 2:52 ` David Gibson
0 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2017-01-12 2:52 UTC (permalink / raw)
To: Eric Blake; +Cc: Jose Ricardo Ziviani, qemu-ppc, qemu-devel, nikunj, bharata
[-- Attachment #1: Type: text/plain, Size: 3059 bytes --]
On Tue, Jan 10, 2017 at 08:34:29AM -0600, Eric Blake wrote:
> On 01/09/2017 08:10 PM, Jose Ricardo Ziviani wrote:
> > Implements 128-bit left shift and right shift as well as their
> > testcases. By design, shift silently mods by 128, so the caller is
> > responsible to assert the shift range if necessary.
> >
> > Left shift sets the overflow flag if any non-zero digit is shifted out.
> >
> > Examples:
> > ulshift(&low, &high, 250, &overflow);
> > equivalent: n << 122
> >
> > urshift(&low, &high, -2);
> > equivalent: n << 126
> >
> > Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> > ---
>
> > +typedef struct {
> > + uint64_t low;
> > + uint64_t high;
> > + uint64_t rlow;
> > + uint64_t rhigh;
> > + int32_t shift;
> > + bool overflow;
> > +} test_data;
> > +
> > +static const test_data test_ltable[] = {
> > + { 0x4C7ULL, 0x0ULL, 0x00000000000004C7ULL,
> > + 0x0000000000000000ULL, 0, false },
>
> I might have laid it out as:
>
> { 0x00000000000004c7ULL, 0x0000000000000000ULL,
> 0x00000000000004c7ULL, 0x0000000000000000ULL,
> 0, false }
>
> to make the pre- and post-shift values line up better. It's not fatal
> to the patch, so it's up to the maintainer if they want a v6 to improve
> the alignment.
host-utils doesn't have a maintainer. So, I'm intending to take it
through my tree with your R-b.
> > + { 0x8888888888888888ULL, 0x9999999999999999ULL,
> > + 0x8000000000000000ULL, 0x9888888888888888ULL, 60, true },
> > + { 0x8888888888888888ULL, 0x9999999999999999ULL,
> > + 0x0000000000000000ULL, 0x8888888888888888ULL, 64, true },
>
> These two are the most legible.
>
> > +};
> > +
> > +static const test_data test_rtable[] = {
>
> > +++ b/util/host-utils.c
> > @@ -161,3 +161,67 @@ int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
> > }
> > #endif
> >
> > +/**
> > + * urshift - 128-bit Unsigned Right Shift.
> > + * @plow: in/out - lower 64-bit integer.
> > + * @phigh: in/out - higher 64-bit integer.
> > + * @shift: in - bytes to shift, between 0 and 127.
> > + *
> > + * Result is zero-extended and stored in plow/phigh, which are
> > + * input/output variables. Shift values outside the range will
> > + * be mod to 128. In other words, the caller is responsible to
> > + * verify/assert both the shift range and plow/phigh pointers.
> > + */
>
> Duplicating docs in the .h and .c doesn't hurt, but risks one getting
> out of date; we have other spots that put the docs in the .h (where
> callers will look up what's available) or the .c (where the
> implementation is there to check against the docs). I don't have any
> strong preference on how to do it, though, so I don't mind leaving it as is.
>
> Reviewed-by: Eric Blake <eblake@redhat.com>
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v5 3/7] ppc: Implement bcds. instruction
2017-01-10 2:10 [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 1/7] host-utils: Move 128-bit guard macro to .c file Jose Ricardo Ziviani
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 2/7] host-utils: Implement unsigned quadword left/right shift and unit tests Jose Ricardo Ziviani
@ 2017-01-10 2:10 ` Jose Ricardo Ziviani
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 4/7] ppc: Implement bcdus. instruction Jose Ricardo Ziviani
` (4 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-10 2:10 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata, eblake
bcds.: Decimal shift. Given two registers vra and vrb, this instruction
shift the vrb value by vra bits into the result register.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 40 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 3 +++
target/ppc/translate/vmx-ops.inc.c | 3 ++-
4 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index f28bf62..36e9b82 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -398,6 +398,7 @@ DEF_HELPER_3(bcdcfsq, i32, avr, avr, i32)
DEF_HELPER_3(bcdctsq, i32, avr, avr, i32)
DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
+DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xsaddqp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 24e5964..26774a6 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -3094,6 +3094,46 @@ uint32_t helper_bcdsetsgn(ppc_avr_t *r, ppc_avr_t *b, uint32_t ps)
return bcd_cmp_zero(r);
}
+uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+ int cr;
+#if defined(HOST_WORDS_BIGENDIAN)
+ int i = a->s8[7];
+#else
+ int i = a->s8[8];
+#endif
+ bool ox_flag = false;
+ int sgnb = bcd_get_sgn(b);
+ ppc_avr_t ret = *b;
+ ret.u64[LO_IDX] &= ~0xf;
+
+ if (bcd_is_valid(b) == false) {
+ return CRF_SO;
+ }
+
+ if (unlikely(i > 31)) {
+ i = 31;
+ } else if (unlikely(i < -31)) {
+ i = -31;
+ }
+
+ if (i > 0) {
+ ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag);
+ } else {
+ urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], -i * 4);
+ }
+ bcd_put_digit(&ret, bcd_preferred_sgn(sgnb, ps), 0);
+
+ *r = ret;
+
+ cr = bcd_cmp_zero(r);
+ if (ox_flag) {
+ cr |= CRF_SO;
+ }
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index e8e527f..84ebb7e 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1016,6 +1016,7 @@ GEN_BCD2(bcdcfsq)
GEN_BCD2(bcdctsq)
GEN_BCD2(bcdsetsgn)
GEN_BCD(bcdcpsgn);
+GEN_BCD(bcds);
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -1090,6 +1091,8 @@ GEN_VXFORM_DUAL(vsubuhs, PPC_ALTIVEC, PPC_NONE, \
bcdsub, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
bcdcpsgn, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
+ bcds, PPC_NONE, PPC2_ISA300)
static void gen_vsbox(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 57dce6e..7b4b009 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -62,7 +62,8 @@ GEN_VXFORM_207(vaddudm, 0, 3),
GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vsubuwm, 0, 18),
-GEN_VXFORM_207(vsubudm, 0, 19),
+GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_300(bcds, 0, 27),
GEN_VXFORM(vmaxub, 1, 0),
GEN_VXFORM(vmaxuh, 1, 1),
GEN_VXFORM(vmaxuw, 1, 2),
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v5 4/7] ppc: Implement bcdus. instruction
2017-01-10 2:10 [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
` (2 preceding siblings ...)
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 3/7] ppc: Implement bcds. instruction Jose Ricardo Ziviani
@ 2017-01-10 2:10 ` Jose Ricardo Ziviani
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 5/7] ppc: Implement bcdsr. instruction Jose Ricardo Ziviani
` (3 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-10 2:10 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata, eblake
bcdus.: Decimal unsigned shift. This instruction works like bcds. but
considers only unsigned BCDs (no sign in least meaning 4 bits).
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 41 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 3 +++
target/ppc/translate/vmx-ops.inc.c | 2 +-
4 files changed, 46 insertions(+), 1 deletion(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 36e9b82..065eb66 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -399,6 +399,7 @@ DEF_HELPER_3(bcdctsq, i32, avr, avr, i32)
DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
+DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xsaddqp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 26774a6..91ae89f 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -3134,6 +3134,47 @@ uint32_t helper_bcds(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+ int cr;
+ int i;
+ int invalid = 0;
+ bool ox_flag = false;
+ ppc_avr_t ret = *b;
+
+ for (i = 0; i < 32; i++) {
+ bcd_get_digit(b, i, &invalid);
+
+ if (unlikely(invalid)) {
+ return CRF_SO;
+ }
+ }
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ i = a->s8[7];
+#else
+ i = a->s8[8];
+#endif
+ if (i >= 32) {
+ ox_flag = true;
+ ret.u64[LO_IDX] = ret.u64[HI_IDX] = 0;
+ } else if (i <= -32) {
+ ret.u64[LO_IDX] = ret.u64[HI_IDX] = 0;
+ } else if (i > 0) {
+ ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag);
+ } else {
+ urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], -i * 4);
+ }
+ *r = ret;
+
+ cr = bcd_cmp_zero(r);
+ if (ox_flag) {
+ cr |= CRF_SO;
+ }
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 84ebb7e..fc54881 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1017,6 +1017,7 @@ GEN_BCD2(bcdctsq)
GEN_BCD2(bcdsetsgn)
GEN_BCD(bcdcpsgn);
GEN_BCD(bcds);
+GEN_BCD(bcdus);
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -1093,6 +1094,8 @@ GEN_VXFORM_DUAL(vaddshs, PPC_ALTIVEC, PPC_NONE, \
bcdcpsgn, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
bcds, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
+ bcdus, PPC_NONE, PPC2_ISA300)
static void gen_vsbox(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 7b4b009..cdd3abe 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -61,7 +61,7 @@ GEN_VXFORM(vadduwm, 0, 2),
GEN_VXFORM_207(vaddudm, 0, 3),
GEN_VXFORM_DUAL(vsububm, bcdadd, 0, 16, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vsubuhm, bcdsub, 0, 17, PPC_ALTIVEC, PPC_NONE),
-GEN_VXFORM(vsubuwm, 0, 18),
+GEN_VXFORM_DUAL(vsubuwm, bcdus, 0, 18, PPC_ALTIVEC, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubudm, bcds, 0, 19, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_300(bcds, 0, 27),
GEN_VXFORM(vmaxub, 1, 0),
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v5 5/7] ppc: Implement bcdsr. instruction
2017-01-10 2:10 [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
` (3 preceding siblings ...)
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 4/7] ppc: Implement bcdus. instruction Jose Ricardo Ziviani
@ 2017-01-10 2:10 ` Jose Ricardo Ziviani
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction Jose Ricardo Ziviani
` (2 subsequent siblings)
7 siblings, 0 replies; 13+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-10 2:10 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata, eblake
bcdsr.: Decimal shift and round. This instruction works like bcds.
however, when performing right shift, 1 will be added to the
result if the last digit was >= 5.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 48 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 2 ++
4 files changed, 52 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 065eb66..d1db462 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -400,6 +400,7 @@ DEF_HELPER_4(bcdcpsgn, i32, avr, avr, avr, i32)
DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
+DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xsaddqp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 91ae89f..b184063 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -3175,6 +3175,54 @@ uint32_t helper_bcdus(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+ int cr;
+ int unused = 0;
+ int invalid = 0;
+ bool ox_flag = false;
+ int sgnb = bcd_get_sgn(b);
+ ppc_avr_t ret = *b;
+ ret.u64[LO_IDX] &= ~0xf;
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ int i = a->s8[7];
+ ppc_avr_t bcd_one = { .u64 = { 0, 0x10 } };
+#else
+ int i = a->s8[8];
+ ppc_avr_t bcd_one = { .u64 = { 0x10, 0 } };
+#endif
+
+ if (bcd_is_valid(b) == false) {
+ return CRF_SO;
+ }
+
+ if (unlikely(i > 31)) {
+ i = 31;
+ } else if (unlikely(i < -31)) {
+ i = -31;
+ }
+
+ if (i > 0) {
+ ulshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], i * 4, &ox_flag);
+ } else {
+ urshift(&ret.u64[LO_IDX], &ret.u64[HI_IDX], -i * 4);
+
+ if (bcd_get_digit(&ret, 0, &invalid) >= 5) {
+ bcd_add_mag(&ret, &ret, &bcd_one, &invalid, &unused);
+ }
+ }
+ bcd_put_digit(&ret, bcd_preferred_sgn(sgnb, ps), 0);
+
+ cr = bcd_cmp_zero(&ret);
+ if (ox_flag) {
+ cr |= CRF_SO;
+ }
+ *r = ret;
+
+ return cr;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index fc54881..451abb5 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1018,6 +1018,7 @@ GEN_BCD2(bcdsetsgn)
GEN_BCD(bcdcpsgn);
GEN_BCD(bcds);
GEN_BCD(bcdus);
+GEN_BCD(bcdsr);
static void gen_xpnd04_1(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index cdd3abe..fa9c996 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -132,6 +132,8 @@ GEN_HANDLER_E_2(vprtybd, 0x4, 0x1, 0x18, 9, 0, PPC_NONE, PPC2_ISA300),
GEN_HANDLER_E_2(vprtybq, 0x4, 0x1, 0x18, 10, 0, PPC_NONE, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubcuw, xpnd04_1, 0, 22, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_300(bcdsr, 0, 23),
+GEN_VXFORM_300(bcdsr, 0, 31),
GEN_VXFORM_DUAL(vaddubs, vmul10uq, 0, 8, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vadduhs, vmul10euq, 0, 9, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vadduws, 0, 10),
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* [Qemu-devel] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction
2017-01-10 2:10 [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
` (4 preceding siblings ...)
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 5/7] ppc: Implement bcdsr. instruction Jose Ricardo Ziviani
@ 2017-01-10 2:10 ` Jose Ricardo Ziviani
2017-01-12 3:10 ` David Gibson
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 7/7] ppc: Implement bcdutrunc. instruction Jose Ricardo Ziviani
2017-01-12 3:17 ` [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part David Gibson
7 siblings, 1 reply; 13+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-10 2:10 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata, eblake
bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
number of bytes to truncate in vra, the return register will have vrb
with such bits truncated.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 37 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 5 +++++
target/ppc/translate/vmx-ops.inc.c | 4 ++--
4 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index d1db462..db17917 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -401,6 +401,7 @@ DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
+DEF_HELPER_4(bcdtrunc, i32, avr, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xsaddqp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index b184063..06b14d5 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -3223,6 +3223,43 @@ uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
return cr;
}
+uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+ uint64_t mask;
+ uint32_t ox_flag = 0;
+#if defined(HOST_WORDS_BIGENDIAN)
+ int i = a->s16[3] + 1;
+#else
+ int i = a->s16[4] + 1;
+#endif
+ ppc_avr_t ret = *b;
+
+ if (bcd_is_valid(b) == false) {
+ return CRF_SO;
+ }
+
+ if (i > 16 && i < 32) {
+ if (ret.u64[HI_IDX] >> (i * 4 - 64)) {
+ ox_flag = CRF_SO;
+ }
+
+ mask = (uint64_t)-1 >> (128 - i * 4);
+ ret.u64[HI_IDX] &= mask;
+ } else if (i >= 0 && i <= 16) {
+ if (ret.u64[HI_IDX] || (i < 16 && ret.u64[LO_IDX] >> (i * 4))) {
+ ox_flag = CRF_SO;
+ }
+
+ mask = (uint64_t)-1 >> (64 - i * 4);
+ ret.u64[LO_IDX] &= mask;
+ ret.u64[HI_IDX] = 0;
+ }
+ bcd_put_digit(&ret, bcd_preferred_sgn(bcd_get_sgn(b), ps), 0);
+ *r = ret;
+
+ return bcd_cmp_zero(&ret) | ox_flag;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 451abb5..1683f42 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1019,6 +1019,7 @@ GEN_BCD(bcdcpsgn);
GEN_BCD(bcds);
GEN_BCD(bcdus);
GEN_BCD(bcdsr);
+GEN_BCD(bcdtrunc);
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -1097,6 +1098,10 @@ GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
bcds, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
bcdus, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
+ bcdtrunc, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
+ bcdtrunc, PPC_NONE, PPC2_ISA300)
static void gen_vsbox(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index fa9c996..e6167a4 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -143,14 +143,14 @@ GEN_VXFORM(vaddsws, 0, 14),
GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vsubuws, 0, 26),
-GEN_VXFORM(vsubsbs, 0, 28),
+GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_NONE, PPC2_ISA300),
GEN_VXFORM(vsubshs, 0, 29),
GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_207(vadduqm, 0, 4),
GEN_VXFORM_207(vaddcuq, 0, 5),
GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_207(vsubuqm, 0, 20),
GEN_VXFORM_207(vsubcuq, 0, 21),
+GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM(vrlb, 2, 0),
GEN_VXFORM(vrlh, 2, 1),
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction Jose Ricardo Ziviani
@ 2017-01-12 3:10 ` David Gibson
0 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2017-01-12 3:10 UTC (permalink / raw)
To: Jose Ricardo Ziviani; +Cc: qemu-ppc, qemu-devel, nikunj, bharata, eblake
[-- Attachment #1: Type: text/plain, Size: 4825 bytes --]
On Tue, Jan 10, 2017 at 12:10:13AM -0200, Jose Ricardo Ziviani wrote:
> bcdtrunc.: Decimal integer truncate. Given a BCD number in vrb and the
> number of bytes to truncate in vra, the return register will have vrb
> with such bits truncated.
>
> Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
> ---
> target/ppc/helper.h | 1 +
> target/ppc/int_helper.c | 37 +++++++++++++++++++++++++++++++++++++
> target/ppc/translate/vmx-impl.inc.c | 5 +++++
> target/ppc/translate/vmx-ops.inc.c | 4 ++--
> 4 files changed, 45 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index d1db462..db17917 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -401,6 +401,7 @@ DEF_HELPER_3(bcdsetsgn, i32, avr, avr, i32)
> DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
> DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
> DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
> +DEF_HELPER_4(bcdtrunc, i32, avr, avr, avr, i32)
>
> DEF_HELPER_2(xsadddp, void, env, i32)
> DEF_HELPER_2(xsaddqp, void, env, i32)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index b184063..06b14d5 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -3223,6 +3223,43 @@ uint32_t helper_bcdsr(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
> return cr;
> }
>
> +uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
> +{
> + uint64_t mask;
> + uint32_t ox_flag = 0;
> +#if defined(HOST_WORDS_BIGENDIAN)
> + int i = a->s16[3] + 1;
> +#else
> + int i = a->s16[4] + 1;
> +#endif
> + ppc_avr_t ret = *b;
> +
> + if (bcd_is_valid(b) == false) {
> + return CRF_SO;
> + }
> +
> + if (i > 16 && i < 32) {
> + if (ret.u64[HI_IDX] >> (i * 4 - 64)) {
> + ox_flag = CRF_SO;
> + }
You can simplify this by just checking ret.u64[HI_IDX] & ~mask before
you apply the mast.
> +
> + mask = (uint64_t)-1 >> (128 - i * 4);
> + ret.u64[HI_IDX] &= mask;
> + } else if (i >= 0 && i <= 16) {
> + if (ret.u64[HI_IDX] || (i < 16 && ret.u64[LO_IDX] >> (i * 4))) {
> + ox_flag = CRF_SO;
> + }
> +
> + mask = (uint64_t)-1 >> (64 - i * 4);
Similarly here.
> + ret.u64[LO_IDX] &= mask;
> + ret.u64[HI_IDX] = 0;
> + }
> + bcd_put_digit(&ret, bcd_preferred_sgn(bcd_get_sgn(b), ps), 0);
> + *r = ret;
> +
> + return bcd_cmp_zero(&ret) | ox_flag;
> +}
> +
> void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
> {
> int i;
> diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
> index 451abb5..1683f42 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -1019,6 +1019,7 @@ GEN_BCD(bcdcpsgn);
> GEN_BCD(bcds);
> GEN_BCD(bcdus);
> GEN_BCD(bcdsr);
> +GEN_BCD(bcdtrunc);
>
> static void gen_xpnd04_1(DisasContext *ctx)
> {
> @@ -1097,6 +1098,10 @@ GEN_VXFORM_DUAL(vsubudm, PPC2_ALTIVEC_207, PPC_NONE, \
> bcds, PPC_NONE, PPC2_ISA300)
> GEN_VXFORM_DUAL(vsubuwm, PPC_ALTIVEC, PPC_NONE, \
> bcdus, PPC_NONE, PPC2_ISA300)
> +GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
> + bcdtrunc, PPC_NONE, PPC2_ISA300)
> +GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
> + bcdtrunc, PPC_NONE, PPC2_ISA300)
>
> static void gen_vsbox(DisasContext *ctx)
> {
> diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
> index fa9c996..e6167a4 100644
> --- a/target/ppc/translate/vmx-ops.inc.c
> +++ b/target/ppc/translate/vmx-ops.inc.c
> @@ -143,14 +143,14 @@ GEN_VXFORM(vaddsws, 0, 14),
> GEN_VXFORM_DUAL(vsububs, bcdadd, 0, 24, PPC_ALTIVEC, PPC_NONE),
> GEN_VXFORM_DUAL(vsubuhs, bcdsub, 0, 25, PPC_ALTIVEC, PPC_NONE),
> GEN_VXFORM(vsubuws, 0, 26),
> -GEN_VXFORM(vsubsbs, 0, 28),
> +GEN_VXFORM_DUAL(vsubsbs, bcdtrunc, 0, 28, PPC_NONE, PPC2_ISA300),
> GEN_VXFORM(vsubshs, 0, 29),
> GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
> GEN_VXFORM_207(vadduqm, 0, 4),
> GEN_VXFORM_207(vaddcuq, 0, 5),
> GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
> -GEN_VXFORM_207(vsubuqm, 0, 20),
> GEN_VXFORM_207(vsubcuq, 0, 21),
> +GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
> GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
> GEN_VXFORM(vrlb, 2, 0),
> GEN_VXFORM(vrlh, 2, 1),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 13+ messages in thread
* [Qemu-devel] [PATCH v5 7/7] ppc: Implement bcdutrunc. instruction
2017-01-10 2:10 [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
` (5 preceding siblings ...)
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 6/7] ppc: Implement bcdtrunc. instruction Jose Ricardo Ziviani
@ 2017-01-10 2:10 ` Jose Ricardo Ziviani
2017-01-12 3:17 ` [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part David Gibson
7 siblings, 0 replies; 13+ messages in thread
From: Jose Ricardo Ziviani @ 2017-01-10 2:10 UTC (permalink / raw)
To: qemu-ppc; +Cc: qemu-devel, david, nikunj, bharata, eblake
bcdutrunc. Decimal unsigned truncate. Works like bcdtrunc. with
unsigned BCD numbers.
Signed-off-by: Jose Ricardo Ziviani <joserz@linux.vnet.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 51 +++++++++++++++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 4 +++
target/ppc/translate/vmx-ops.inc.c | 2 +-
4 files changed, 57 insertions(+), 1 deletion(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index db17917..c2e6b42 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -402,6 +402,7 @@ DEF_HELPER_4(bcds, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdus, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdsr, i32, avr, avr, avr, i32)
DEF_HELPER_4(bcdtrunc, i32, avr, avr, avr, i32)
+DEF_HELPER_4(bcdutrunc, i32, avr, avr, avr, i32)
DEF_HELPER_2(xsadddp, void, env, i32)
DEF_HELPER_2(xsaddqp, void, env, i32)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 06b14d5..6fe3a73 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -3260,6 +3260,57 @@ uint32_t helper_bcdtrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
return bcd_cmp_zero(&ret) | ox_flag;
}
+uint32_t helper_bcdutrunc(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t ps)
+{
+ int i;
+ uint64_t mask;
+ uint32_t ox_flag = 0;
+ int invalid = 0;
+ ppc_avr_t ret = *b;
+
+ for (i = 0; i < 32; i++) {
+ bcd_get_digit(b, i, &invalid);
+
+ if (unlikely(invalid)) {
+ return CRF_SO;
+ }
+ }
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ i = a->s16[3];
+#else
+ i = a->s16[4];
+#endif
+ if (i > 16 && i < 33) {
+ if (ret.u64[HI_IDX] >> (i * 4 - 64)) {
+ ox_flag = CRF_SO;
+ }
+
+ mask = (uint64_t)-1 >> (128 - i * 4);
+ ret.u64[HI_IDX] &= mask;
+ } else if (i > 0 && i <= 16) {
+ if (ret.u64[HI_IDX] || (i < 16 && ret.u64[LO_IDX] >> (i * 4))) {
+ ox_flag = CRF_SO;
+ }
+
+ mask = (uint64_t)-1 >> (64 - i * 4);
+ ret.u64[LO_IDX] &= mask;
+ ret.u64[HI_IDX] = 0;
+ } else if (i == 0) {
+ if (ret.u64[HI_IDX] || ret.u64[LO_IDX]) {
+ ox_flag = CRF_SO;
+ }
+ ret.u64[HI_IDX] = ret.u64[LO_IDX] = 0;
+ }
+
+ *r = ret;
+ if (r->u64[HI_IDX] == 0 && r->u64[LO_IDX] == 0) {
+ return ox_flag | CRF_EQ;
+ }
+
+ return ox_flag | CRF_GT;
+}
+
void helper_vsbox(ppc_avr_t *r, ppc_avr_t *a)
{
int i;
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 1683f42..3cb6fc2 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -1020,6 +1020,7 @@ GEN_BCD(bcds);
GEN_BCD(bcdus);
GEN_BCD(bcdsr);
GEN_BCD(bcdtrunc);
+GEN_BCD(bcdutrunc);
static void gen_xpnd04_1(DisasContext *ctx)
{
@@ -1102,6 +1103,9 @@ GEN_VXFORM_DUAL(vsubsbs, PPC_ALTIVEC, PPC_NONE, \
bcdtrunc, PPC_NONE, PPC2_ISA300)
GEN_VXFORM_DUAL(vsubuqm, PPC2_ALTIVEC_207, PPC_NONE, \
bcdtrunc, PPC_NONE, PPC2_ISA300)
+GEN_VXFORM_DUAL(vsubcuq, PPC2_ALTIVEC_207, PPC_NONE, \
+ bcdutrunc, PPC_NONE, PPC2_ISA300)
+
static void gen_vsbox(DisasContext *ctx)
{
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index e6167a4..139f80c 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -149,8 +149,8 @@ GEN_VXFORM_DUAL(vsubsws, xpnd04_2, 0, 30, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM_207(vadduqm, 0, 4),
GEN_VXFORM_207(vaddcuq, 0, 5),
GEN_VXFORM_DUAL(vaddeuqm, vaddecuq, 30, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
-GEN_VXFORM_207(vsubcuq, 0, 21),
GEN_VXFORM_DUAL(vsubuqm, bcdtrunc, 0, 20, PPC2_ALTIVEC_207, PPC2_ISA300),
+GEN_VXFORM_DUAL(vsubcuq, bcdutrunc, 0, 21, PPC2_ALTIVEC_207, PPC2_ISA300),
GEN_VXFORM_DUAL(vsubeuqm, vsubecuq, 31, 0xFF, PPC_NONE, PPC2_ALTIVEC_207),
GEN_VXFORM(vrlb, 2, 0),
GEN_VXFORM(vrlh, 2, 1),
--
2.7.4
^ permalink raw reply related [flat|nested] 13+ messages in thread* Re: [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part
2017-01-10 2:10 [Qemu-devel] [PATCH v5 0/7] POWER9 TCG enablements - BCD functions - final part Jose Ricardo Ziviani
` (6 preceding siblings ...)
2017-01-10 2:10 ` [Qemu-devel] [PATCH v5 7/7] ppc: Implement bcdutrunc. instruction Jose Ricardo Ziviani
@ 2017-01-12 3:17 ` David Gibson
7 siblings, 0 replies; 13+ messages in thread
From: David Gibson @ 2017-01-12 3:17 UTC (permalink / raw)
To: Jose Ricardo Ziviani; +Cc: qemu-ppc, qemu-devel, nikunj, bharata, eblake
[-- Attachment #1: Type: text/plain, Size: 2493 bytes --]
On Tue, Jan 10, 2017 at 12:10:07AM -0200, Jose Ricardo Ziviani wrote:
> v5:
> - removes 'unlikely' gcc branch pred. hints from not unlikely places
> - adds comments in host-utils functions
> - adds more test cases for shift functions
> - handles "shift backwards" with signed shifts
> - rebases branch
>
> v4:
> - improves functions to behave exactly like the target
>
> v3:
> - moves shift functions to host-utils.c and added config_int128 guard
> - changes Makefile to always compile host-utils.c
> - redesigns bcd[u]trunc to use bitwise operations
> - removes "target-ppc: Implement bcd_is_valid function" (merged)
>
> v2:
> - bcd[s,sr,us] uses 1 byte for shifting instead of 4 bytes
> - left/right functions in host-utils are out of CONFIG_INT128
> - fixes overflowing issue in left shift and added a testcase
>
> This serie contains 5 new instructions for POWER9 ISA3.0, left/right shifts for
> unsigned quadwords and a small improvement to check whether a bcd value is
> valid or not.
Patches 1-5 applied to ppc-for-2.9, remainder left with a suggestion
for improvement.
>
> bcds.: Decimal signed shift
> bcdus.: Decimal unsigned shift
> bcdsr.: Decimal shift and round
> bcdtrunc.: Decimal signed trucate
> bcdutrunc.: Decimal unsigned truncate
>
> Jose Ricardo Ziviani (7):
> host-utils: Move 128-bit guard macro to .c file
> host-utils: Implement unsigned quadword left/right shift and unit
> tests
> ppc: Implement bcds. instruction
> ppc: Implement bcdus. instruction
> ppc: Implement bcdsr. instruction
> ppc: Implement bcdtrunc. instruction
> ppc: Implement bcdutrunc. instruction
>
> include/qemu/host-utils.h | 27 +++++
> target/ppc/helper.h | 5 +
> target/ppc/int_helper.c | 217 ++++++++++++++++++++++++++++++++++++
> target/ppc/translate/vmx-impl.inc.c | 16 +++
> target/ppc/translate/vmx-ops.inc.c | 13 ++-
> tests/Makefile.include | 5 +-
> tests/test-shift128.c | 139 +++++++++++++++++++++++
> util/Makefile.objs | 2 +-
> util/host-utils.c | 66 +++++++++++
> 9 files changed, 483 insertions(+), 7 deletions(-)
> create mode 100644 tests/test-shift128.c
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 13+ messages in thread