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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: atar4qemu@gmail.com, mark.cave-ayland@ilande.co.uk,
	peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode
Date: Wed, 11 Jan 2017 18:55:46 -0800	[thread overview]
Message-ID: <20170112025606.27332-11-rth@twiddle.net> (raw)
In-Reply-To: <20170112025606.27332-1-rth@twiddle.net>

From: Artyom Tarasenko <atar4qemu@gmail.com>

Accordinf to UA2005, 9.3.3 "Address Space Identifiers",

"In hyperprivileged mode, all instruction fetches and loads and stores with implicit
ASIs use a physical address, regardless of the value of TL".

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Message-Id: <6c5b3d85dcfabe9935687ecb986e80ce71f89cab.1484165352.git.atar4qemu@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target/sparc/cpu.h       | 4 ++--
 target/sparc/translate.c | 6 +++++-
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 113ae33..4f709e1 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -716,10 +716,10 @@ static inline int cpu_mmu_index(CPUSPARCState *env, bool ifetch)
         ? (env->lsu & IMMU_E) == 0 || (env->pstate & PS_RED) != 0
         : (env->lsu & DMMU_E) == 0) {
         return MMU_PHYS_IDX;
-    } else if (env->tl > 0) {
-        return MMU_NUCLEUS_IDX;
     } else if (cpu_hypervisor_mode(env)) {
         return MMU_HYPV_IDX;
+    } else if (env->tl > 0) {
+        return MMU_NUCLEUS_IDX;
     } else if (cpu_supervisor_mode(env)) {
         return MMU_KERNEL_IDX;
     } else {
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index b898898..82f9965 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -2142,7 +2142,11 @@ static DisasASI get_asi(DisasContext *dc, int insn, TCGMemOp memop)
         case ASI_TWINX_NL:
         case ASI_NUCLEUS_QUAD_LDD:
         case ASI_NUCLEUS_QUAD_LDD_L:
-            mem_idx = MMU_NUCLEUS_IDX;
+            if (hypervisor(dc)) {
+                mem_idx = MMU_HYPV_IDX;
+            } else {
+                mem_idx = MMU_NUCLEUS_IDX;
+            }
             break;
         case ASI_AIUP:  /* As if user primary */
         case ASI_AIUPL: /* As if user primary LE */
-- 
2.9.3

  parent reply	other threads:[~2017-01-12  2:56 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-12  2:55 [Qemu-devel] [PULL 00/30] target-sparc sun4v support Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR Richard Henderson
2017-01-12  2:55 ` Richard Henderson [this message]
2017-01-12  2:55 ` [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs " Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 26/30] target-sparc: store the UA2005 entries in sun4u format Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine Richard Henderson
2017-01-12  4:24 ` [Qemu-devel] [PULL 00/30] target-sparc sun4v support no-reply
2017-01-13 14:01 ` Peter Maydell
2017-01-16  9:44   ` Artyom Tarasenko
  -- strict thread matches above, loose matches on Subject: below --
2017-01-18 22:38 Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode Artyom Tarasenko

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