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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: atar4qemu@gmail.com, mark.cave-ayland@ilande.co.uk,
	peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps
Date: Wed, 11 Jan 2017 18:55:47 -0800	[thread overview]
Message-ID: <20170112025606.27332-12-rth@twiddle.net> (raw)
In-Reply-To: <20170112025606.27332-1-rth@twiddle.net>

From: Artyom Tarasenko <atar4qemu@gmail.com>

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Message-Id: <7edada4d1c26562843de80c9eb2339ca591f883b.1484165352.git.atar4qemu@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 target/sparc/cpu.h          |  1 +
 target/sparc/int64_helper.c | 37 ++++++++++++++++++++++++++++++++-----
 target/sparc/win_helper.c   |  6 ++++++
 3 files changed, 39 insertions(+), 5 deletions(-)

diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 4f709e1..f26fdcf 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -79,6 +79,7 @@
 #define TT_FILL     0xc0
 #define TT_WOTHER   (1 << 5)
 #define TT_TRAP     0x100
+#define TT_HTRAP    0x180
 #endif
 
 #define PSR_NEG_SHIFT 23
diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c
index 29360fa..8300eb4 100644
--- a/target/sparc/int64_helper.c
+++ b/target/sparc/int64_helper.c
@@ -78,8 +78,10 @@ void sparc_cpu_do_interrupt(CPUState *cs)
         static int count;
         const char *name;
 
-        if (intno < 0 || intno >= 0x180) {
+        if (intno < 0 || intno >= 0x1ff) {
             name = "Unknown";
+        } else if (intno >= 0x180) {
+            name = "Hyperprivileged Trap Instruction";
         } else if (intno >= 0x100) {
             name = "Trap Instruction";
         } else if (intno >= 0xc0) {
@@ -135,16 +137,36 @@ void sparc_cpu_do_interrupt(CPUState *cs)
     tsptr->tnpc = env->npc;
     tsptr->tt = intno;
 
+    if (cpu_has_hypervisor(env)) {
+        env->htstate[env->tl] = env->hpstate;
+        /* XXX OpenSPARC T1 - UltraSPARC T3 have MAXPTL=2
+           but this may change in the future */
+        if (env->tl > 2) {
+            env->hpstate |= HS_PRIV;
+        }
+    }
+
     switch (intno) {
     case TT_IVEC:
-        cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
+        if (!cpu_has_hypervisor(env)) {
+            cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_IG);
+        }
         break;
     case TT_TFAULT:
     case TT_DFAULT:
     case TT_TMISS ... TT_TMISS + 3:
     case TT_DMISS ... TT_DMISS + 3:
     case TT_DPROT ... TT_DPROT + 3:
-        cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
+        if (cpu_has_hypervisor(env)) {
+            env->hpstate |= HS_PRIV;
+            env->pstate = PS_PEF | PS_PRIV;
+        } else {
+            cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_MG);
+        }
+        break;
+    case TT_INSN_REAL_TRANSLATION_MISS ... TT_DATA_REAL_TRANSLATION_MISS:
+    case TT_HTRAP ... TT_HTRAP + 127:
+        env->hpstate |= HS_PRIV;
         break;
     default:
         cpu_change_pstate(env, PS_PEF | PS_PRIV | PS_AG);
@@ -158,8 +180,13 @@ void sparc_cpu_do_interrupt(CPUState *cs)
     } else if ((intno & 0x1c0) == TT_FILL) {
         cpu_set_cwp(env, cpu_cwp_inc(env, env->cwp + 1));
     }
-    env->pc = env->tbr  & ~0x7fffULL;
-    env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
+
+    if (cpu_hypervisor_mode(env)) {
+        env->pc = (env->htba & ~0x3fffULL) | (intno << 5);
+    } else {
+        env->pc = env->tbr  & ~0x7fffULL;
+        env->pc |= ((env->tl > 1) ? 1 << 14 : 0) | (intno << 5);
+    }
     env->npc = env->pc + 4;
     cs->exception_index = -1;
 }
diff --git a/target/sparc/win_helper.c b/target/sparc/win_helper.c
index 2d5b546..45ee4e6 100644
--- a/target/sparc/win_helper.c
+++ b/target/sparc/win_helper.c
@@ -366,6 +366,9 @@ void helper_done(CPUSPARCState *env)
     env->asi = (tsptr->tstate >> 24) & 0xff;
     cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
     cpu_put_cwp64(env, tsptr->tstate & 0xff);
+    if (cpu_has_hypervisor(env)) {
+        env->hpstate = env->htstate[env->tl];
+    }
     env->tl--;
 
     trace_win_helper_done(env->tl);
@@ -387,6 +390,9 @@ void helper_retry(CPUSPARCState *env)
     env->asi = (tsptr->tstate >> 24) & 0xff;
     cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
     cpu_put_cwp64(env, tsptr->tstate & 0xff);
+    if (cpu_has_hypervisor(env)) {
+        env->hpstate = env->htstate[env->tl];
+    }
     env->tl--;
 
     trace_win_helper_retry(env->tl);
-- 
2.9.3

  parent reply	other threads:[~2017-01-12  2:56 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-12  2:55 [Qemu-devel] [PULL 00/30] target-sparc sun4v support Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode Richard Henderson
2017-01-12  2:55 ` Richard Henderson [this message]
2017-01-12  2:55 ` [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs " Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages Richard Henderson
2017-01-12  2:55 ` [Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 26/30] target-sparc: store the UA2005 entries in sun4u format Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c Richard Henderson
2017-01-12  2:56 ` [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine Richard Henderson
2017-01-12  4:24 ` [Qemu-devel] [PULL 00/30] target-sparc sun4v support no-reply
2017-01-13 14:01 ` Peter Maydell
2017-01-16  9:44   ` Artyom Tarasenko
  -- strict thread matches above, loose matches on Subject: below --
2017-01-18 22:38 Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps Artyom Tarasenko

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