From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55361) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cRVYk-0007gR-32 for qemu-devel@nongnu.org; Wed, 11 Jan 2017 21:56:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cRVYj-0006hE-8t for qemu-devel@nongnu.org; Wed, 11 Jan 2017 21:56:14 -0500 Received: from mail-qt0-x243.google.com ([2607:f8b0:400d:c0d::243]:33531) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1cRVYj-0006h7-4s for qemu-devel@nongnu.org; Wed, 11 Jan 2017 21:56:13 -0500 Received: by mail-qt0-x243.google.com with SMTP id n13so849234qtc.0 for ; Wed, 11 Jan 2017 18:56:12 -0800 (PST) Sender: Richard Henderson From: Richard Henderson Date: Wed, 11 Jan 2017 18:55:37 -0800 Message-Id: <20170112025606.27332-2-rth@twiddle.net> In-Reply-To: <20170112025606.27332-1-rth@twiddle.net> References: <20170112025606.27332-1-rth@twiddle.net> Subject: [Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: atar4qemu@gmail.com, mark.cave-ayland@ilande.co.uk, peter.maydell@linaro.org From: Artyom Tarasenko while IMMU/DMMU is disabled - ignore MMU-faults in hypervisorv mode or if CPU doesn't have hypervisor - signal TT_INSN_REAL_TRANSLATION_MISS/TT_DATA_REAL_TRANSLATION_MISS otherwise Signed-off-by: Artyom Tarasenko Message-Id: Signed-off-by: Richard Henderson --- target/sparc/cpu.h | 2 ++ target/sparc/ldst_helper.c | 15 +++++++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5fb0ed1..e0b2806 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -68,6 +68,8 @@ #define TT_DATA_ACCESS 0x32 #define TT_UNALIGNED 0x34 #define TT_PRIV_ACT 0x37 +#define TT_INSN_REAL_TRANSLATION_MISS 0x3e +#define TT_DATA_REAL_TRANSLATION_MISS 0x3f #define TT_EXTINT 0x40 #define TT_IVEC 0x60 #define TT_TMISS 0x64 diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index de7d53a..fdca87f 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -1664,14 +1664,25 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, { SPARCCPU *cpu = SPARC_CPU(cs); CPUSPARCState *env = &cpu->env; - int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; #ifdef DEBUG_UNASSIGNED printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx "\n", addr, env->pc); #endif - cpu_raise_exception_ra(env, tt, GETPC()); + if (is_exec) { /* XXX has_hypervisor */ + if (env->lsu & (IMMU_E)) { + cpu_raise_exception_ra(env, TT_CODE_ACCESS, GETPC()); + } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { + cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, GETPC()); + } + } else { + if (env->lsu & (DMMU_E)) { + cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); + } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { + cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, GETPC()); + } + } } #endif #endif -- 2.9.3