From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: atar4qemu@gmail.com, mark.cave-ayland@ilande.co.uk,
peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs
Date: Wed, 11 Jan 2017 18:55:55 -0800 [thread overview]
Message-ID: <20170112025606.27332-20-rth@twiddle.net> (raw)
In-Reply-To: <20170112025606.27332-1-rth@twiddle.net>
From: Artyom Tarasenko <atar4qemu@gmail.com>
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Message-Id: <146ff5800a7da7599439d69c4bd907a0b51747aa.1484165352.git.atar4qemu@gmail.com>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
linux-user/main.c | 2 +-
target/sparc/cpu.h | 48 +++++++++++++++++-----------------------------
target/sparc/ldst_helper.c | 8 ++++----
target/sparc/machine.c | 4 ++--
4 files changed, 25 insertions(+), 37 deletions(-)
diff --git a/linux-user/main.c b/linux-user/main.c
index c1d5eb4..94a636f 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -1166,7 +1166,7 @@ void cpu_loop (CPUSPARCState *env)
/* XXX: check env->error_code */
info.si_code = TARGET_SEGV_MAPERR;
if (trapnr == TT_DFAULT)
- info._sifields._sigfault._addr = env->dmmuregs[4];
+ info._sifields._sigfault._addr = env->dmmu.mmuregs[4];
else
info._sifields._sigfault._addr = cpu_tsptr(env)->tpc;
queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h
index 6fc81e8..8ce7197 100644
--- a/target/sparc/cpu.h
+++ b/target/sparc/cpu.h
@@ -404,7 +404,22 @@ struct CPUTimer
typedef struct CPUTimer CPUTimer;
typedef struct CPUSPARCState CPUSPARCState;
-
+#if defined(TARGET_SPARC64)
+typedef union {
+ uint64_t mmuregs[16];
+ struct {
+ uint64_t tsb_tag_target;
+ uint64_t mmu_primary_context;
+ uint64_t mmu_secondary_context;
+ uint64_t sfsr;
+ uint64_t sfar;
+ uint64_t tsb;
+ uint64_t tag_access;
+ uint64_t virtual_watchpoint;
+ uint64_t physical_watchpoint;
+ };
+} SparcV9MMU;
+#endif
struct CPUSPARCState {
target_ulong gregs[8]; /* general registers */
target_ulong *regwptr; /* pointer to current register window */
@@ -454,35 +469,8 @@ struct CPUSPARCState {
uint64_t lsu;
#define DMMU_E 0x8
#define IMMU_E 0x4
- //typedef struct SparcMMU
- union {
- uint64_t immuregs[16];
- struct {
- uint64_t tsb_tag_target;
- uint64_t unused_mmu_primary_context; // use DMMU
- uint64_t unused_mmu_secondary_context; // use DMMU
- uint64_t sfsr;
- uint64_t sfar;
- uint64_t tsb;
- uint64_t tag_access;
- uint64_t virtual_watchpoint;
- uint64_t physical_watchpoint;
- } immu;
- };
- union {
- uint64_t dmmuregs[16];
- struct {
- uint64_t tsb_tag_target;
- uint64_t mmu_primary_context;
- uint64_t mmu_secondary_context;
- uint64_t sfsr;
- uint64_t sfar;
- uint64_t tsb;
- uint64_t tag_access;
- uint64_t virtual_watchpoint;
- uint64_t physical_watchpoint;
- } dmmu;
- };
+ SparcV9MMU immu;
+ SparcV9MMU dmmu;
SparcTLBEntry itlb[64];
SparcTLBEntry dtlb[64];
uint32_t mmu_version;
diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c
index 8cc8bb1..8e01260 100644
--- a/target/sparc/ldst_helper.c
+++ b/target/sparc/ldst_helper.c
@@ -1481,7 +1481,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int reg = (addr >> 3) & 0xf;
uint64_t oldreg;
- oldreg = env->immuregs[reg];
+ oldreg = env->immu.mmuregs[reg];
switch (reg) {
case 0: /* RO */
return;
@@ -1512,7 +1512,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
break;
}
- if (oldreg != env->immuregs[reg]) {
+ if (oldreg != env->immu.mmuregs[reg]) {
DPRINTF_MMU("immu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
PRIx64 "\n", reg, oldreg, env->immuregs[reg]);
}
@@ -1546,7 +1546,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
int reg = (addr >> 3) & 0xf;
uint64_t oldreg;
- oldreg = env->dmmuregs[reg];
+ oldreg = env->dmmu.mmuregs[reg];
switch (reg) {
case 0: /* RO */
case 4:
@@ -1589,7 +1589,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
break;
}
- if (oldreg != env->dmmuregs[reg]) {
+ if (oldreg != env->dmmu.mmuregs[reg]) {
DPRINTF_MMU("dmmu change reg[%d]: 0x%016" PRIx64 " -> 0x%016"
PRIx64 "\n", reg, oldreg, env->dmmuregs[reg]);
}
diff --git a/target/sparc/machine.c b/target/sparc/machine.c
index aea6397..39e262c 100644
--- a/target/sparc/machine.c
+++ b/target/sparc/machine.c
@@ -148,8 +148,8 @@ const VMStateDescription vmstate_sparc_cpu = {
VMSTATE_UINT64_ARRAY(env.mmubpregs, SPARCCPU, 4),
#else
VMSTATE_UINT64(env.lsu, SPARCCPU),
- VMSTATE_UINT64_ARRAY(env.immuregs, SPARCCPU, 16),
- VMSTATE_UINT64_ARRAY(env.dmmuregs, SPARCCPU, 16),
+ VMSTATE_UINT64_ARRAY(env.immu.mmuregs, SPARCCPU, 16),
+ VMSTATE_UINT64_ARRAY(env.dmmu.mmuregs, SPARCCPU, 16),
VMSTATE_STRUCT_ARRAY(env.itlb, SPARCCPU, 64, 0,
vmstate_tlb_entry, SparcTLBEntry),
VMSTATE_STRUCT_ARRAY(env.dtlb, SPARCCPU, 64, 0,
--
2.9.3
next prev parent reply other threads:[~2017-01-12 2:56 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-12 2:55 [Qemu-devel] [PULL 00/30] target-sparc sun4v support Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 02/30] target-sparc: store cpu super- and hypervisor flags in TB Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 03/30] target-sparc: use explicit mmu register pointers Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 04/30] target-sparc: add UA2005 TTE bit #defines Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 05/30] target-sparc: add UltraSPARC T1 TLB #defines Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 08/30] target-sparc: implement UA2005 scratchpad registers Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 10/30] target-sparc: hypervisor mode takes over nucleus mode Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 11/30] target-sparc: implement UA2005 hypervisor traps Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 12/30] target-sparc: implement UA2005 GL register Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 14/30] target-sparc: fix immediate UA2005 traps Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 15/30] target-sparc: use direct address translation in hyperprivileged mode Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 16/30] target-sparc: allow priveleged ASIs " Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 18/30] target-sparc: replace the last tlb entry when no free entries left Richard Henderson
2017-01-12 2:55 ` Richard Henderson [this message]
2017-01-12 2:55 ` [Qemu-devel] [PULL 20/30] target-sparc: implement UA2005 TSB Pointers Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 21/30] target-sparc: simplify ultrasparc_tsb_pointer Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 22/30] target-sparc: allow 256M sized pages Richard Henderson
2017-01-12 2:55 ` [Qemu-devel] [PULL 23/30] target-sparc: implement auto-demapping for UA2005 CPUs Richard Henderson
2017-01-12 2:56 ` [Qemu-devel] [PULL 24/30] target-sparc: add more registers to dump_mmu Richard Henderson
2017-01-12 2:56 ` [Qemu-devel] [PULL 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) Richard Henderson
2017-01-12 2:56 ` [Qemu-devel] [PULL 26/30] target-sparc: store the UA2005 entries in sun4u format Richard Henderson
2017-01-12 2:56 ` [Qemu-devel] [PULL 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs Richard Henderson
2017-01-12 2:56 ` [Qemu-devel] [PULL 28/30] target-sparc: implement sun4v RTC Richard Henderson
2017-01-12 2:56 ` [Qemu-devel] [PULL 29/30] target-sparc: move common cpu initialisation routines to sparc64.c Richard Henderson
2017-01-12 2:56 ` [Qemu-devel] [PULL 30/30] target-sparc: fix up niagara machine Richard Henderson
2017-01-12 4:24 ` [Qemu-devel] [PULL 00/30] target-sparc sun4v support no-reply
2017-01-13 14:01 ` Peter Maydell
2017-01-16 9:44 ` Artyom Tarasenko
-- strict thread matches above, loose matches on Subject: below --
2017-01-18 22:38 Artyom Tarasenko
2017-01-18 22:38 ` [Qemu-devel] [PULL 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs Artyom Tarasenko
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