From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org,
bharata@linux.vnet.ibm.com
Subject: Re: [Qemu-devel] [PATCH 03/11] target-ppc: Add xsiexpdp instruction
Date: Thu, 12 Jan 2017 16:11:51 +1100 [thread overview]
Message-ID: <20170112051151.GP14026@umbus.fritz.box> (raw)
In-Reply-To: <8760lkvpz1.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me>
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On Thu, Jan 12, 2017 at 10:23:22AM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Tue, Jan 10, 2017 at 02:20:35PM +0530, Nikunj A Dadhania wrote:
> >> xsiexpdp: VSX Scalar Insert Exponent Double Precision
> >>
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> ---
> >> target/ppc/translate/vsx-impl.inc.c | 20 ++++++++++++++++++++
> >> target/ppc/translate/vsx-ops.inc.c | 1 +
> >> 2 files changed, 21 insertions(+)
> >>
> >> diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c
> >> index 2d9fe50..2d09225 100644
> >> --- a/target/ppc/translate/vsx-impl.inc.c
> >> +++ b/target/ppc/translate/vsx-impl.inc.c
> >> @@ -1243,6 +1243,26 @@ static void gen_xsxexpqp(DisasContext *ctx)
> >> tcg_gen_movi_i64(xtl, 0);
> >> }
> >>
> >> +static void gen_xsiexpdp(DisasContext *ctx)
> >> +{
> >> + TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
> >> + TCGv ra = cpu_gpr[rA(ctx->opcode)];
> >> + TCGv rb = cpu_gpr[rB(ctx->opcode)];
> >> + TCGv_i64 t0;
> >> +
> >> + if (unlikely(!ctx->vsx_enabled)) {
> >> + gen_exception(ctx, POWERPC_EXCP_VSXU);
> >> + return;
> >> + }
> >> + t0 = tcg_temp_new_i64();
> >> + tcg_gen_andi_i64(xth, ra, 0x800FFFFFFFFFFFFF);
> >> + tcg_gen_andi_i64(t0, rb, 0x7FF);
> >> + tcg_gen_shli_i64(t0, t0, 52);
> >> + tcg_gen_or_i64(xth, xth, t0);
> >> + /* dword[1] is undefined */
> >
> > According to the ISA doc I have, dword[1] is set to 0 rather than
> > being undefined.
>
> Referring to xsiexpdp on page 570:
>
> "The contents of doubleword element 1 of VSR[XT] are
> undefined."
>
> The revision that I have is dated November 30, 2015
Ah, sorry. I think I just misread all those "U"s in the pseudo-code
as "0"s. I'll blame the fact I'm using the little laptop screen,
since I've left my home office to escape the heat.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2017-01-12 5:27 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-01-10 8:50 [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11 Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 01/11] target-ppc: xscvqpdp zero VSR Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 02/11] softfloat: Fix the default qNAN for target-ppc Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 03/11] target-ppc: Add xsiexpdp instruction Nikunj A Dadhania
2017-01-12 2:47 ` David Gibson
2017-01-12 4:53 ` Nikunj A Dadhania
2017-01-12 5:11 ` David Gibson [this message]
2017-01-10 8:50 ` [Qemu-devel] [PATCH 04/11] target-ppc: Add xsiexpqp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 05/11] target-ppc: Add xviexpsp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 06/11] target-ppc: Add xviexpdp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 07/11] target-ppc: Add xvxexpsp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 08/11] target-ppc: Add xvxexpdp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 09/11] target-ppc: Add xvxsigsp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 10/11] target-ppc: Add xvxsigdp instruction Nikunj A Dadhania
2017-01-10 8:50 ` [Qemu-devel] [PATCH 11/11] target-ppc: Add xscvqps[d, w]z instructions Nikunj A Dadhania
2017-01-12 2:51 ` [Qemu-devel] [PATCH 00/11] POWER9 TCG enablements - part11 David Gibson
2017-01-12 5:38 ` David Gibson
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