* [Qemu-devel] [PULL 1/4] tcg/s390: Fix merge error with facilities
2017-01-13 20:05 [Qemu-devel] [PULL 0/4] tcg fixes Richard Henderson
@ 2017-01-13 20:05 ` Richard Henderson
2017-01-13 20:05 ` [Qemu-devel] [PULL 2/4] target/arm: Fix ubfx et al for aarch64 Richard Henderson
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2017-01-13 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The variable was renamed s390_facilities.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/s390/tcg-target.inc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c
index 0682d01..a679280 100644
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.inc.c
@@ -1096,7 +1096,7 @@ static int tgen_cmp(TCGContext *s, TCGType type, TCGCond c, TCGReg r1,
/* If we only got here because of load-and-test,
and we couldn't use that, then we need to load
the constant into a register. */
- if (!(facilities & FACILITY_EXT_IMM)) {
+ if (!(s390_facilities & FACILITY_EXT_IMM)) {
c2 = TCG_TMP0;
tcg_out_movi(s, type, c2, 0);
goto do_reg;
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PULL 3/4] tcg/aarch64: Fix addsub2 for 0+C
2017-01-13 20:05 [Qemu-devel] [PULL 0/4] tcg fixes Richard Henderson
2017-01-13 20:05 ` [Qemu-devel] [PULL 1/4] tcg/s390: Fix merge error with facilities Richard Henderson
2017-01-13 20:05 ` [Qemu-devel] [PULL 2/4] target/arm: Fix ubfx et al for aarch64 Richard Henderson
@ 2017-01-13 20:05 ` Richard Henderson
2017-01-13 20:05 ` [Qemu-devel] [PULL 4/4] tcg/aarch64: Fix tcg_out_movi Richard Henderson
2017-01-16 12:41 ` [Qemu-devel] [PULL 0/4] tcg fixes Peter Maydell
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2017-01-13 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-stable
When al == xzr, we cannot use addi/subi because that encodes xsp.
Force a zero into the temp register for that (rare) case.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20161207180727.6286-2-rth@twiddle.net>
---
tcg/aarch64/tcg-target.inc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index 585b0d6..deb5967 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -964,6 +964,15 @@ static inline void tcg_out_addsub2(TCGContext *s, int ext, TCGReg rl,
insn = I3401_SUBSI;
bl = -bl;
}
+ if (unlikely(al == TCG_REG_XZR)) {
+ /* ??? We want to allow al to be zero for the benefit of
+ negation via subtraction. However, that leaves open the
+ possibility of adding 0+const in the low part, and the
+ immediate add instructions encode XSP not XZR. Don't try
+ anything more elaborate here than loading another zero. */
+ al = TCG_REG_TMP;
+ tcg_out_movi(s, ext, al, 0);
+ }
tcg_out_insn_3401(s, insn, ext, rl, al, bl);
} else {
tcg_out_insn_3502(s, sub ? I3502_SUBS : I3502_ADDS, ext, rl, al, bl);
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread* [Qemu-devel] [PULL 4/4] tcg/aarch64: Fix tcg_out_movi
2017-01-13 20:05 [Qemu-devel] [PULL 0/4] tcg fixes Richard Henderson
` (2 preceding siblings ...)
2017-01-13 20:05 ` [Qemu-devel] [PULL 3/4] tcg/aarch64: Fix addsub2 for 0+C Richard Henderson
@ 2017-01-13 20:05 ` Richard Henderson
2017-01-16 12:41 ` [Qemu-devel] [PULL 0/4] tcg fixes Peter Maydell
4 siblings, 0 replies; 6+ messages in thread
From: Richard Henderson @ 2017-01-13 20:05 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, qemu-stable
There were some patterns, like 0x0000_ffff_ffff_00ff, for which we
would select to begin a multi-insn sequence with MOVN, but would
fail to set the 0x0000 lane back from 0xffff.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <rth@twiddle.net>
Message-Id: <20161207180727.6286-3-rth@twiddle.net>
---
tcg/aarch64/tcg-target.inc.c | 57 +++++++++++++++++++-------------------------
1 file changed, 24 insertions(+), 33 deletions(-)
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
index deb5967..6d227a5 100644
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.inc.c
@@ -580,11 +580,9 @@ static void tcg_out_logicali(TCGContext *s, AArch64Insn insn, TCGType ext,
static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
tcg_target_long value)
{
- AArch64Insn insn;
int i, wantinv, shift;
tcg_target_long svalue = value;
tcg_target_long ivalue = ~value;
- tcg_target_long imask;
/* For 32-bit values, discard potential garbage in value. For 64-bit
values within [2**31, 2**32-1], we can create smaller sequences by
@@ -630,42 +628,35 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
/* Would it take fewer insns to begin with MOVN? For the value and its
inverse, count the number of 16-bit lanes that are 0. */
- for (i = wantinv = imask = 0; i < 64; i += 16) {
+ for (i = wantinv = 0; i < 64; i += 16) {
tcg_target_long mask = 0xffffull << i;
- if ((value & mask) == 0) {
- wantinv -= 1;
- }
- if ((ivalue & mask) == 0) {
- wantinv += 1;
- imask |= mask;
- }
+ wantinv -= ((value & mask) == 0);
+ wantinv += ((ivalue & mask) == 0);
}
- /* If we had more 0xffff than 0x0000, invert VALUE and use MOVN. */
- insn = I3405_MOVZ;
- if (wantinv > 0) {
- value = ivalue;
- insn = I3405_MOVN;
- }
-
- /* Find the lowest lane that is not 0x0000. */
- shift = ctz64(value) & (63 & -16);
- tcg_out_insn_3405(s, insn, type, rd, value >> shift, shift);
-
- if (wantinv > 0) {
- /* Re-invert the value, so MOVK sees non-inverted bits. */
- value = ~value;
- /* Clear out all the 0xffff lanes. */
- value ^= imask;
- }
- /* Clear out the lane that we just set. */
- value &= ~(0xffffUL << shift);
-
- /* Iterate until all lanes have been set, and thus cleared from VALUE. */
- while (value) {
+ if (wantinv <= 0) {
+ /* Find the lowest lane that is not 0x0000. */
shift = ctz64(value) & (63 & -16);
- tcg_out_insn(s, 3405, MOVK, type, rd, value >> shift, shift);
+ tcg_out_insn(s, 3405, MOVZ, type, rd, value >> shift, shift);
+ /* Clear out the lane that we just set. */
value &= ~(0xffffUL << shift);
+ /* Iterate until all non-zero lanes have been processed. */
+ while (value) {
+ shift = ctz64(value) & (63 & -16);
+ tcg_out_insn(s, 3405, MOVK, type, rd, value >> shift, shift);
+ value &= ~(0xffffUL << shift);
+ }
+ } else {
+ /* Like above, but with the inverted value and MOVN to start. */
+ shift = ctz64(ivalue) & (63 & -16);
+ tcg_out_insn(s, 3405, MOVN, type, rd, ivalue >> shift, shift);
+ ivalue &= ~(0xffffUL << shift);
+ while (ivalue) {
+ shift = ctz64(ivalue) & (63 & -16);
+ /* Provide MOVK with the non-inverted value. */
+ tcg_out_insn(s, 3405, MOVK, type, rd, ~(ivalue >> shift), shift);
+ ivalue &= ~(0xffffUL << shift);
+ }
}
}
--
2.9.3
^ permalink raw reply related [flat|nested] 6+ messages in thread