qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: David Gibson <david@gibson.dropbear.id.au>
To: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Cc: qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [RFC PATCH 03/17] target/ppc: Add pcr_supported to POWER9 cpu class definition
Date: Tue, 17 Jan 2017 08:21:25 +1100	[thread overview]
Message-ID: <20170116212125.GD15853@umbus> (raw)
In-Reply-To: <1484288903-18807-4-git-send-email-sjitindarsingh@gmail.com>

[-- Attachment #1: Type: text/plain, Size: 2071 bytes --]

On Fri, Jan 13, 2017 at 05:28:09PM +1100, Suraj Jitindar Singh wrote:
> pcr_supported is used to define the supported PCR values for a given
> processor. A POWER9 processor can support 3.00, 2.07, 2.06 and 2.05
> compatibility modes, thus we set this accordingly.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>

This looks fine to go ahead now, so I've merged it to ppc-for-2.9.

> ---
>  target/ppc/cpu.h            | 1 +
>  target/ppc/translate_init.c | 2 ++
>  2 files changed, 3 insertions(+)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 2a50c43..afb7ddb 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2250,6 +2250,7 @@ enum {
>      PCR_COMPAT_2_05     = 1ull << (63-62),
>      PCR_COMPAT_2_06     = 1ull << (63-61),
>      PCR_COMPAT_2_07     = 1ull << (63-60),
> +    PCR_COMPAT_3_00     = 1ull << (63-59),
>      PCR_VEC_DIS         = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
>      PCR_VSX_DIS         = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
>      PCR_TM_DIS          = 1ull << (63-2), /* Trans. memory disable (POWER8) */
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 626e031..bfc1f24 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8797,6 +8797,8 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
>      dc->props = powerpc_servercpu_properties;
>      pcc->pvr_match = ppc_pvr_match_power9;
>      pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06 | PCR_COMPAT_2_07;
> +    pcc->pcr_supported = PCR_COMPAT_3_00 | PCR_COMPAT_2_07 | PCR_COMPAT_2_06 |
> +                         PCR_COMPAT_2_05;
>      pcc->init_proc = init_proc_POWER9;
>      pcc->check_pow = check_pow_nocheck;
>      pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]

  reply	other threads:[~2017-01-16 23:31 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-01-13  6:28 [Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support Suraj Jitindar Singh
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 01/17] powerpc/cpu-models: rename ISAv3.00 logical PVR definition Suraj Jitindar Singh
2017-01-16  2:16   ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 02/17] hw/ppc/spapr: Add POWER9 to pseries cpu models Suraj Jitindar Singh
2017-01-16 12:11   ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 03/17] target/ppc: Add pcr_supported to POWER9 cpu class definition Suraj Jitindar Singh
2017-01-16 21:21   ` David Gibson [this message]
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 04/17] target/ppc/POWER9: Add ISAv3.00 MMU definition Suraj Jitindar Singh
2017-01-16 21:36   ` David Gibson
2017-01-17  0:33     ` Suraj Jitindar Singh
2017-01-23  5:01       ` Suraj Jitindar Singh
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 05/17] target/ppc/POWER9: Adapt LPCR handling for POWER9 Suraj Jitindar Singh
2017-01-16 21:40   ` David Gibson
2017-01-17  0:48     ` Suraj Jitindar Singh
2017-01-17  4:37       ` David Gibson
2017-01-23  4:19         ` Suraj Jitindar Singh
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 06/17] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv Suraj Jitindar Singh
2017-02-01  0:50   ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 07/17] target/ppc/POWER9: Add partition table pointer to sPAPRMachineState Suraj Jitindar Singh
2017-02-01  4:04   ` David Gibson
2017-02-09  2:57     ` Suraj Jitindar Singh
2017-02-10  0:11       ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 08/17] target/ppc/POWER9: Add external partition table pointer to cpu state Suraj Jitindar Singh
2017-02-01  4:09   ` David Gibson
2017-02-09  2:58     ` Suraj Jitindar Singh
2017-02-10  0:11       ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 09/17] target/ppc/POWER9: Remove SDR1 register Suraj Jitindar Singh
2017-02-01  4:16   ` David Gibson
2017-02-09  3:00     ` Suraj Jitindar Singh
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 10/17] target/ppc/POWER9: Add POWER9 mmu fault handler Suraj Jitindar Singh
2017-02-01  4:23   ` David Gibson
2017-02-09  3:04     ` Suraj Jitindar Singh
2017-02-10  0:16       ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 11/17] target/ppc/POWER9: Update to new pte format for POWER9 accesses Suraj Jitindar Singh
2017-02-01  4:28   ` David Gibson
2017-02-09  3:08     ` Suraj Jitindar Singh
2017-02-09 23:47       ` Suraj Jitindar Singh
2017-02-10  0:21         ` David Gibson
2017-02-10  1:05           ` Suraj Jitindar Singh
2017-02-10  2:24             ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 12/17] target/ppc/POWER9: Add POWER9 pa-features definition Suraj Jitindar Singh
2017-02-01  4:29   ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 13/17] target/ppc/POWER9: Add cpu_has_work function for POWER9 Suraj Jitindar Singh
2017-02-01  4:34   ` David Gibson
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 14/17] target/ppc/debug: Print LPCR register value if register exists Suraj Jitindar Singh
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 15/17] tcg/POWER9: NOOP the cp_abort instruction Suraj Jitindar Singh
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 16/17] target/ppc/mmu_hash64: Fix printing unsigned as signed int Suraj Jitindar Singh
2017-01-13  6:28 ` [Qemu-devel] [RFC PATCH 17/17] target/ppc/mmu_hash64: Fix incorrect shift value in amr calculation Suraj Jitindar Singh
2017-01-13  6:55 ` [Qemu-devel] [RFC PATCH 00/17] target/ppc: Implement POWER9 pseries tcg legacy kernel support no-reply
2017-02-01  1:04   ` David Gibson
2017-02-09  3:09     ` Suraj Jitindar Singh
2017-02-01  2:16 ` David Gibson
2017-02-01  2:22   ` David Gibson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20170116212125.GD15853@umbus \
    --to=david@gibson.dropbear.id.au \
    --cc=agraf@suse.de \
    --cc=qemu-devel@nongnu.org \
    --cc=qemu-ppc@nongnu.org \
    --cc=sjitindarsingh@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).