From: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org
Subject: Re: [Qemu-devel] [PATCH v2 1/2] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode
Date: Sat, 4 Feb 2017 15:14:13 +0100 [thread overview]
Message-ID: <20170204141413.GO9606@toto> (raw)
In-Reply-To: <1486144135-4894-2-git-send-email-peter.maydell@linaro.org>
On Fri, Feb 03, 2017 at 05:48:54PM +0000, Peter Maydell wrote:
> In the ARM ldr/str decode path, rather than directly testing
> "insn & (1 << 21)" and "insn & (1 << 24)", abstract these
> bits out into wbit and pbit local flags. (We will want to
> do more tests against them to determine whether we need to
> provide syndrome information.)
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> target/arm/translate.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 493c627..175b4c1 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -8782,6 +8782,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> } else {
> int address_offset;
> bool load = insn & (1 << 20);
> + bool wbit = insn & (1 << 21);
> + bool pbit = insn & (1 << 24);
> bool doubleword = false;
> /* Misc load/store */
> rn = (insn >> 16) & 0xf;
> @@ -8799,8 +8801,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> }
>
> addr = load_reg(s, rn);
> - if (insn & (1 << 24))
> + if (pbit) {
> gen_add_datah_offset(s, insn, 0, addr);
> + }
> address_offset = 0;
>
> if (doubleword) {
> @@ -8849,10 +8852,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
> ensure correct behavior with overlapping index registers.
> ldrd with base writeback is undefined if the
> destination and index registers overlap. */
> - if (!(insn & (1 << 24))) {
> + if (!pbit) {
> gen_add_datah_offset(s, insn, address_offset, addr);
> store_reg(s, rn, addr);
> - } else if (insn & (1 << 21)) {
> + } else if (wbit) {
> if (address_offset)
> tcg_gen_addi_i32(addr, addr, address_offset);
> store_reg(s, rn, addr);
> --
> 2.7.4
>
next prev parent reply other threads:[~2017-02-04 14:14 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-03 17:48 [Qemu-devel] [PATCH v2 0/2] target/arm: Support EL1 AArch32 guest under AArch64 EL2 Peter Maydell
2017-02-03 17:48 ` [Qemu-devel] [PATCH v2 1/2] target/arm: Abstract out pbit/wbit tests in ARM ldr/str decode Peter Maydell
2017-02-04 14:14 ` Edgar E. Iglesias [this message]
2017-02-03 17:48 ` [Qemu-devel] [PATCH v2 2/2] target/arm: A32, T32: Create Instruction Syndromes for Data Aborts Peter Maydell
2017-02-04 14:31 ` Edgar E. Iglesias
2017-02-06 14:53 ` Peter Maydell
2017-02-06 15:06 ` Edgar E. Iglesias
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