[Qemu-devel] [PATCH v3 00/16] target-m68k: implement 680x0 FPU

[Laurent Vivier <laurent@vivier.eu>]

This series modifies the original ColdFire FPU implementation
to use floatx80 instead of float64 internally as this
is the native datatype for 680x0. I didn't keep the float64
type for ColdFire, but if someone thinks it's required I
can update this series in this way.

The series also adds the FPU status and control registers and
several floating point instructions.

The floatx80 datatype used here is not exactly the same as the
one used by 680x0 for its extended precision data type, because
normally the signaling bit of 680x0 NAN is the MSB of the mantissa
minus one and in floatx80 it is the MSB.

We also add the gdb server parts to read the new FPU registers.
A strange thing happens here: while the gdb client running remotely
from a debian etch-m68k has no issue working with 96bit FPU registers
(the 680x0 extended precision data type), new gdbs (from a debian unstable
and gdb for cross-compiled environment) don't expect this FPU registers
size. But it seems like a bug in gdb, not in this implementation.

After this series is applied, qemu-m68k can run a debian etch-m68k
or a debian unstable chroot.

v3:
    fix fsave opcode
    Add comment to define "unnormalized" number
    Correctly define pickNaN()

v2:
    complete rework of the series
    force single precision in ColdFire mode
    add "forced" precision instructions (fsmove, fdmove, fsadd, ...)
    fixed Fcc.

Laurent Vivier (16):
  softfloat: define 680x0 specific values
  softloat: disable floatx80_invalid_encoding() for m68k
  target-m68k: move FPU helpers to fpu_helper.c
  target-m68k: define ext_opsize
  target-m68k: use floatx80 internally
  target-m68k: add FPCR and FPSR
  target-m68k: manage FPU exceptions
  target-m68k: define 96bit FP registers for gdb on 680x0
  target-m68k: add fmovem
  target-m68k: add fscc.
  target-m68k: add fmovecr
  target-m68k: add fscale, fgetman, fgetexp and fmod
  target-m68k: add fsglmul and fsgldiv
  target-m68k: add explicit single and double precision operations
  target-m68k: add more FPU instructions
  target-m68k: add fsincos

 configure                  |    2 +-
 fpu/softfloat-specialize.h |   34 +-
 fpu/softfloat.c            |   31 ++
 gdb-xml/m68k-fp.xml        |   21 +
 include/fpu/softfloat.h    |   15 -
 target/m68k/Makefile.objs  |    2 +-
 target/m68k/cpu.c          |   13 +-
 target/m68k/cpu.h          |   75 ++-
 target/m68k/fpu_helper.c   |  972 ++++++++++++++++++++++++++++++++
 target/m68k/helper.c       |  165 +++---
 target/m68k/helper.h       |   73 ++-
 target/m68k/qregs.def      |    4 +-
 target/m68k/translate.c    | 1318 +++++++++++++++++++++++++++++++++-----------
 13 files changed, 2254 insertions(+), 471 deletions(-)
 create mode 100644 gdb-xml/m68k-fp.xml
 create mode 100644 target/m68k/fpu_helper.c

-- 
2.9.3