From: P J P <ppandit@redhat.com>
To: Qemu Developers <qemu-devel@nongnu.org>
Cc: Alistair Francis <alistair23@gmail.com>,
Peter Maydell <peter.maydell@linaro.org>,
Wjjzhang <wjjzhang@tencent.com>, Jiang Xin <jiangxin1@huawei.com>,
"Edgar E . Iglesias" <edgar.iglesias@gmail.com>,
Prasad J Pandit <pjp@fedoraproject.org>
Subject: [Qemu-devel] [PATCH v2 0/3] sd: sdhci: correct transfer mode register usage
Date: Wed, 8 Feb 2017 12:12:09 +0530 [thread overview]
Message-ID: <20170208064212.25307-1-ppandit@redhat.com> (raw)
From: Prasad J Pandit <pjp@fedoraproject.org>
Hello,
In SDHCI protocol, the 'Block Count Enable' bit of the Transfer Mode
register is used to control 's->blkcnt' value. One, this bit is not
relevant in single block transfers. Second, Transfer Mode register
value could be set such that 's->blkcnt' would not see an update
during multi block transfers. Thus leading to an infinite loop.
This patch set attempts to correct 'Block Count Enable' bit usage.
This series incorporates changes suggested in patch set v1:
-> https://lists.gnu.org/archive/html/qemu-devel/2017-01/msg06476.html
Thank you.
--
Prasad J Pandit (3):
sd: sdhci: check transfer mode register in multi block transfer
sd: sdhci: conditionally invoke multi block transfer
sd: sdhci: Remove block count enable check in single block transfers
hw/sd/sdhci.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
--
2.9.3
next reply other threads:[~2017-02-08 6:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-08 6:42 P J P [this message]
2017-02-08 6:42 ` [Qemu-devel] [PATCH v2 1/3] sd: sdhci: check transfer mode register in multi block transfer P J P
2017-02-10 22:45 ` Alistair Francis
2017-02-08 6:42 ` [Qemu-devel] [PATCH v2 2/3] sd: sdhci: conditionally invoke " P J P
2017-02-10 23:10 ` Alistair Francis
2017-02-08 6:42 ` [Qemu-devel] [PATCH v2 3/3] sd: sdhci: Remove block count enable check in single block transfers P J P
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