From: David Gibson <david@gibson.dropbear.id.au>
To: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Cc: qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org,
sam.bobroff@au1.ibm.com
Subject: Re: [Qemu-devel] [QEMU-PPC] [PATCH V2 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9
Date: Mon, 13 Feb 2017 15:34:33 +1100 [thread overview]
Message-ID: <20170213043433.GV25381@umbus> (raw)
In-Reply-To: <1486704360-27361-10-git-send-email-sjitindarsingh@gmail.com>
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On Fri, Feb 10, 2017 at 04:25:59PM +1100, Suraj Jitindar Singh wrote:
> The cpu has work function is used to mask interrupts used to determine
> if there is work for the cpu based on the LPCR. Add a function to do this
> for POWER9 and add it to the POWER9 cpu definition. This is similar to that
> for POWER8 except using the LPCR bits as defined for POWER9.
>
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target/ppc/translate_init.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index a3a23d8..cc8ab1f 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8776,10 +8776,54 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
> return false;
> }
>
> +static bool cpu_has_work_POWER9(CPUState *cs)
> +{
> + PowerPCCPU *cpu = POWERPC_CPU(cs);
> + CPUPPCState *env = &cpu->env;
> +
> + if (cs->halted) {
> + if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
> + return false;
> + }
> + /* External Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
> + (env->spr[SPR_LPCR] & LPCR_EEE)) {
> + return true;
> + }
> + /* Decrementer Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
> + (env->spr[SPR_LPCR] & LPCR_DEE)) {
> + return true;
> + }
> + /* Machine Check or Hypervisor Maintenance Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
> + 1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
> + return true;
> + }
> + /* Privileged Doorbell Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
> + (env->spr[SPR_LPCR] & LPCR_PDEE)) {
> + return true;
> + }
> + /* Hypervisor Doorbell Exception */
> + if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
> + (env->spr[SPR_LPCR] & LPCR_HDEE)) {
> + return true;
> + }
> + if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
> + return true;
> + }
> + return false;
> + } else {
> + return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
> + }
> +}
> +
> POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
> + CPUClass *cc = CPU_CLASS(oc);
>
> dc->fw_name = "PowerPC,POWER9";
> dc->desc = "POWER9";
> @@ -8790,6 +8834,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
> PCR_COMPAT_2_05;
> pcc->init_proc = init_proc_POWER9;
> pcc->check_pow = check_pow_nocheck;
> + cc->has_work = cpu_has_work_POWER9;
> pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
> PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
> PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2017-02-13 4:40 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-10 5:25 [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 02/10] target/ppc: Fix LPCR DPFD mask define Suraj Jitindar Singh
2017-02-13 1:59 ` David Gibson
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 05/10] target/ppc: Add patb_entry to sPAPRMachineState Suraj Jitindar Singh
2017-02-13 2:17 ` David Gibson
2017-02-13 3:40 ` Suraj Jitindar Singh
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 06/10] target/ppc: Don't use SDR1 when running under a POWER9 cpu model Suraj Jitindar Singh
2017-02-13 3:44 ` David Gibson
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler Suraj Jitindar Singh
2017-02-13 4:06 ` David Gibson
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 08/10] target/ppc/POWER9: Add POWER9 pa-features definition Suraj Jitindar Singh
2017-02-13 4:33 ` David Gibson
2017-02-10 5:25 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9 Suraj Jitindar Singh
2017-02-13 4:34 ` David Gibson [this message]
2017-02-10 5:26 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models Suraj Jitindar Singh
2017-02-13 4:35 ` David Gibson
2017-02-10 5:28 ` [Qemu-devel] [QEMU-PPC] [PATCH V2 00/10] target/ppc: Implement POWER9 pseries tcg Suraj Jitindar Singh
2017-02-10 5:49 ` Suraj Jitindar Singh
2017-02-10 5:43 ` no-reply
2017-02-13 4:40 ` David Gibson
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