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From: "Alex Bennée" <alex.bennee@linaro.org>
To: peter.maydell@linaro.org, rth@twiddle.net
Cc: mttcg@listserver.greensocs.com, qemu-devel@nongnu.org,
	fred.konrad@greensocs.com, a.rigo@virtualopensystems.com,
	cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com,
	mark.burton@greensocs.com, pbonzini@redhat.com,
	jan.kiszka@siemens.com, serge.fdrv@gmail.com,
	bamvor.zhangjian@linaro.org,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: [Qemu-devel] [PATCH v12 04/24] tcg: move TCG_MO/BAR types into own file
Date: Mon, 13 Feb 2017 12:09:57 +0000	[thread overview]
Message-ID: <20170213121017.12907-5-alex.bennee@linaro.org> (raw)
In-Reply-To: <20170213121017.12907-1-alex.bennee@linaro.org>

We'll be using the memory ordering definitions to define values for
both the host and guest. To avoid fighting with circular header
dependencies just move these types into their own minimal header.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>

---
v8
  - add clarifying comment about the form TCG_MO_A_B
---
 tcg/tcg-mo.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 tcg/tcg.h    | 18 +-----------------
 2 files changed, 49 insertions(+), 17 deletions(-)
 create mode 100644 tcg/tcg-mo.h

diff --git a/tcg/tcg-mo.h b/tcg/tcg-mo.h
new file mode 100644
index 0000000000..c2c55704e1
--- /dev/null
+++ b/tcg/tcg-mo.h
@@ -0,0 +1,48 @@
+/*
+ * Tiny Code Generator for QEMU
+ *
+ * Copyright (c) 2008 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#ifndef TCG_MO_H
+#define TCG_MO_H
+
+typedef enum {
+    /* Used to indicate the type of accesses on which ordering
+       is to be ensured.  Modeled after SPARC barriers.
+
+       This is of the form TCG_MO_A_B where A is before B in program order.
+    */
+    TCG_MO_LD_LD  = 0x01,
+    TCG_MO_ST_LD  = 0x02,
+    TCG_MO_LD_ST  = 0x04,
+    TCG_MO_ST_ST  = 0x08,
+    TCG_MO_ALL    = 0x0F,  /* OR of the above */
+
+    /* Used to indicate the kind of ordering which is to be ensured by the
+       instruction.  These types are derived from x86/aarch64 instructions.
+       It should be noted that these are different from C11 semantics.  */
+    TCG_BAR_LDAQ  = 0x10,  /* Following ops will not come forward */
+    TCG_BAR_STRL  = 0x20,  /* Previous ops will not be delayed */
+    TCG_BAR_SC    = 0x30,  /* No ops cross barrier; OR of the above */
+} TCGBar;
+
+#endif /* TCG_MO_H */
diff --git a/tcg/tcg.h b/tcg/tcg.h
index 631c6f69b1..f946452049 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -29,6 +29,7 @@
 #include "cpu.h"
 #include "exec/tb-context.h"
 #include "qemu/bitops.h"
+#include "tcg-mo.h"
 #include "tcg-target.h"
 
 /* XXX: make safe guess about sizes */
@@ -498,23 +499,6 @@ static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
 #define TCG_CALL_DUMMY_TCGV     MAKE_TCGV_I32(-1)
 #define TCG_CALL_DUMMY_ARG      ((TCGArg)(-1))
 
-typedef enum {
-    /* Used to indicate the type of accesses on which ordering
-       is to be ensured.  Modeled after SPARC barriers.  */
-    TCG_MO_LD_LD  = 0x01,
-    TCG_MO_ST_LD  = 0x02,
-    TCG_MO_LD_ST  = 0x04,
-    TCG_MO_ST_ST  = 0x08,
-    TCG_MO_ALL    = 0x0F,  /* OR of the above */
-
-    /* Used to indicate the kind of ordering which is to be ensured by the
-       instruction.  These types are derived from x86/aarch64 instructions.
-       It should be noted that these are different from C11 semantics.  */
-    TCG_BAR_LDAQ  = 0x10,  /* Following ops will not come forward */
-    TCG_BAR_STRL  = 0x20,  /* Previous ops will not be delayed */
-    TCG_BAR_SC    = 0x30,  /* No ops cross barrier; OR of the above */
-} TCGBar;
-
 /* Conditions.  Note that these are laid out for easy manipulation by
    the functions below:
      bit 0 is used for inverting;
-- 
2.11.0

  parent reply	other threads:[~2017-02-13 12:10 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-13 12:09 [Qemu-devel] [PATCH v12 00/24] MTTCG Base enabling patches with ARM enablement Alex Bennée
2017-02-13 12:09 ` [Qemu-devel] [PATCH v12 01/24] docs: new design document multi-thread-tcg.txt Alex Bennée
2017-02-13 12:09 ` [Qemu-devel] [PATCH v12 02/24] mttcg: translate-all: Enable locking debug in a debug build Alex Bennée
2017-02-13 12:09 ` [Qemu-devel] [PATCH v12 03/24] mttcg: Add missing tb_lock/unlock() in cpu_exec_step() Alex Bennée
2017-02-13 12:09 ` Alex Bennée [this message]
2017-02-13 12:09 ` [Qemu-devel] [PATCH v12 05/24] tcg: add options for enabling MTTCG Alex Bennée
2017-02-13 12:09 ` [Qemu-devel] [PATCH v12 06/24] tcg: add kick timer for single-threaded vCPU emulation Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 07/24] tcg: rename tcg_current_cpu to tcg_current_rr_cpu Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 08/24] tcg: drop global lock during TCG code execution Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 09/24] tcg: remove global exit_request Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 10/24] tcg: enable tb_lock() for SoftMMU Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 11/24] tcg: enable thread-per-vCPU Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 12/24] tcg: handle EXCP_ATOMIC exception for system emulation Alex Bennée
2017-02-13 19:19   ` Richard Henderson
2017-02-13 19:33     ` Pranith Kumar
2017-02-13 19:57       ` Richard Henderson
2017-02-14 10:50     ` Alex Bennée
2017-02-15 21:53       ` Richard Henderson
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 13/24] cputlb: add assert_cpu_is_self checks Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 14/24] cputlb: tweak qemu_ram_addr_from_host_nofail reporting Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 15/24] cputlb: introduce tlb_flush_* async work Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 16/24] cputlb and arm/sparc targets: convert mmuidx flushes from varg to bitmap Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 17/24] cputlb: add tlb_flush_by_mmuidx async routines Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 18/24] cputlb: atomically update tlb fields used by tlb_reset_dirty Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 19/24] cputlb: introduce tlb_flush_*_all_cpus[_synced] Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 20/24] target-arm/powerctl: defer cpu reset work to CPU context Alex Bennée
2017-02-17 13:07   ` Peter Maydell
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 21/24] target-arm: don't generate WFE/YIELD calls for MTTCG Alex Bennée
2017-02-17 17:17   ` Pranith Kumar
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 22/24] target-arm: ensure all cross vCPUs TLB flushes complete Alex Bennée
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 23/24] hw/misc/imx6_src: defer clearing of SRC_SCR reset bits Alex Bennée
2017-02-17 13:08   ` Peter Maydell
2017-02-13 12:10 ` [Qemu-devel] [PATCH v12 24/24] tcg: enable MTTCG by default for ARM on x86 hosts Alex Bennée

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