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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 03/24] linux-user: Fix openrisc cpu_loop
Date: Tue, 14 Feb 2017 08:25:15 +1100	[thread overview]
Message-ID: <20170213212536.31871-4-rth@twiddle.net> (raw)
In-Reply-To: <20170213212536.31871-1-rth@twiddle.net>

We need to handle EXCP_DEBUG and EXCP_INTERRUPT.
We need to send signals to the guest using queue_signal.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 linux-user/main.c | 95 ++++++++++++++++++++++++-------------------------------
 1 file changed, 41 insertions(+), 54 deletions(-)

diff --git a/linux-user/main.c b/linux-user/main.c
index e588f58..001f71c 100644
--- a/linux-user/main.c
+++ b/linux-user/main.c
@@ -2574,52 +2574,17 @@ kuser_fail:
 void cpu_loop(CPUOpenRISCState *env)
 {
     CPUState *cs = CPU(openrisc_env_get_cpu(env));
-    int trapnr, gdbsig;
+    int trapnr;
     abi_long ret;
+    target_siginfo_t info;
 
     for (;;) {
         cpu_exec_start(cs);
         trapnr = cpu_exec(cs);
         cpu_exec_end(cs);
         process_queued_cpu_work(cs);
-        gdbsig = 0;
 
         switch (trapnr) {
-        case EXCP_RESET:
-            qemu_log_mask(CPU_LOG_INT, "\nReset request, exit, pc is %#x\n", env->pc);
-            exit(EXIT_FAILURE);
-            break;
-        case EXCP_BUSERR:
-            qemu_log_mask(CPU_LOG_INT, "\nBus error, exit, pc is %#x\n", env->pc);
-            gdbsig = TARGET_SIGBUS;
-            break;
-        case EXCP_DPF:
-        case EXCP_IPF:
-            cpu_dump_state(cs, stderr, fprintf, 0);
-            gdbsig = TARGET_SIGSEGV;
-            break;
-        case EXCP_TICK:
-            qemu_log_mask(CPU_LOG_INT, "\nTick time interrupt pc is %#x\n", env->pc);
-            break;
-        case EXCP_ALIGN:
-            qemu_log_mask(CPU_LOG_INT, "\nAlignment pc is %#x\n", env->pc);
-            gdbsig = TARGET_SIGBUS;
-            break;
-        case EXCP_ILLEGAL:
-            qemu_log_mask(CPU_LOG_INT, "\nIllegal instructionpc is %#x\n", env->pc);
-            gdbsig = TARGET_SIGILL;
-            break;
-        case EXCP_INT:
-            qemu_log_mask(CPU_LOG_INT, "\nExternal interruptpc is %#x\n", env->pc);
-            break;
-        case EXCP_DTLBMISS:
-        case EXCP_ITLBMISS:
-            qemu_log_mask(CPU_LOG_INT, "\nTLB miss\n");
-            break;
-        case EXCP_RANGE:
-            qemu_log_mask(CPU_LOG_INT, "\nRange\n");
-            gdbsig = TARGET_SIGSEGV;
-            break;
         case EXCP_SYSCALL:
             env->pc += 4;   /* 0xc00; */
             ret = do_syscall(env,
@@ -2636,32 +2601,54 @@ void cpu_loop(CPUOpenRISCState *env)
                 env->gpr[11] = ret;
             }
             break;
+        case EXCP_DPF:
+        case EXCP_IPF:
+        case EXCP_RANGE:
+            info.si_signo = TARGET_SIGSEGV;
+            info.si_errno = 0;
+            info.si_code = TARGET_SEGV_MAPERR;
+            info._sifields._sigfault._addr = env->pc;
+            queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+            break;
+        case EXCP_ALIGN:
+            info.si_signo = TARGET_SIGBUS;
+            info.si_errno = 0;
+            info.si_code = TARGET_BUS_ADRALN;
+            info._sifields._sigfault._addr = env->pc;
+            queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+            break;
+        case EXCP_ILLEGAL:
+            info.si_signo = TARGET_SIGILL;
+            info.si_errno = 0;
+            info.si_code = TARGET_ILL_ILLOPC;
+            info._sifields._sigfault._addr = env->pc;
+            queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+            break;
         case EXCP_FPE:
-            qemu_log_mask(CPU_LOG_INT, "\nFloating point error\n");
+            info.si_signo = TARGET_SIGFPE;
+            info.si_errno = 0;
+            info.si_code = 0;
+            info._sifields._sigfault._addr = env->pc;
+            queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
             break;
-        case EXCP_TRAP:
-            qemu_log_mask(CPU_LOG_INT, "\nTrap\n");
-            gdbsig = TARGET_SIGTRAP;
+        case EXCP_INTERRUPT:
+            /* We processed the pending cpu work above.  */
             break;
-        case EXCP_NR:
-            qemu_log_mask(CPU_LOG_INT, "\nNR\n");
+        case EXCP_DEBUG:
+            trapnr = gdb_handlesig(cs, TARGET_SIGTRAP);
+            if (trapnr) {
+                info.si_signo = trapnr;
+                info.si_errno = 0;
+                info.si_code = TARGET_TRAP_BRKPT;
+                queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
+            }
             break;
         case EXCP_ATOMIC:
             cpu_exec_step_atomic(cs);
             break;
         default:
-            EXCP_DUMP(env, "\nqemu: unhandled CPU exception %#x - aborting\n",
-                     trapnr);
-            gdbsig = TARGET_SIGILL;
-            break;
-        }
-        if (gdbsig) {
-            gdb_handlesig(cs, gdbsig);
-            if (gdbsig != TARGET_SIGTRAP) {
-                exit(EXIT_FAILURE);
-            }
+            g_assert_not_reached();
         }
-
         process_pending_signals(env);
     }
 }
-- 
2.9.3

  parent reply	other threads:[~2017-02-13 21:26 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-13 21:25 [Qemu-devel] [PULL 00/24] target/openrisc patches Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 01/24] target/openrisc: Rename the cpu from or32 to or1k Richard Henderson
2017-02-13 21:25 ` Richard Henderson [this message]
2017-02-13 21:25 ` [Qemu-devel] [PULL 04/24] linux-user: Honor CLONE_SETTLS for openrisc Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 05/24] target/openrisc: Fix exception handling status registers Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 06/24] target/openrisc: Implement lwa, swa Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 07/24] target/openrisc: Tidy insn dumping Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 08/24] target/openrisc: Rationalize immediate extraction Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 09/24] target/openrisc: Streamline arithmetic and OVE Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 10/24] target/openrisc: Put SR[OVE] in TB flags Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 11/24] target/openrisc: Invert the decoding in dec_calc Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 12/24] target/openrisc: Keep SR_F in a separate variable Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 13/24] target/openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 14/24] target/openrisc: Use movcond where appropriate Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 15/24] target/openrisc: Set flags on helpers Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 16/24] target/openrisc: Enable trap, csync, msync, psync for user mode Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 17/24] target/openrisc: Implement msync Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 18/24] target/openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 19/24] target/openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 20/24] target/openrisc: Fix madd Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 21/24] target/openrisc: Optimize l.jal to next Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 22/24] target/openrisc: Tidy ppc/npc implementation Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 23/24] target/openrisc: Tidy handling of delayed branches Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 24/24] target/openrisc: Optimize for r0 being zero Richard Henderson
2017-02-14 11:01 ` [Qemu-devel] [PULL 00/24] target/openrisc patches Peter Maydell

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