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From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 04/24] linux-user: Honor CLONE_SETTLS for openrisc
Date: Tue, 14 Feb 2017 08:25:16 +1100	[thread overview]
Message-ID: <20170213212536.31871-5-rth@twiddle.net> (raw)
In-Reply-To: <20170213212536.31871-1-rth@twiddle.net>

Threads work much better when you set the TLS register.
This was fixed in the upstream kernel for Linux 4.9.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 linux-user/openrisc/target_cpu.h | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/linux-user/openrisc/target_cpu.h b/linux-user/openrisc/target_cpu.h
index a21ed1a..f283d96 100644
--- a/linux-user/openrisc/target_cpu.h
+++ b/linux-user/openrisc/target_cpu.h
@@ -30,9 +30,7 @@ static inline void cpu_clone_regs(CPUOpenRISCState *env, target_ulong newsp)
 
 static inline void cpu_set_tls(CPUOpenRISCState *env, target_ulong newtls)
 {
-    /* Linux kernel 3.10 does not pay any attention to CLONE_SETTLS
-     * in copy_thread(), so QEMU need not do so either.
-     */
+    env->gpr[10] = newtls;
 }
 
 #endif
-- 
2.9.3

  parent reply	other threads:[~2017-02-13 21:26 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-02-13 21:25 [Qemu-devel] [PULL 00/24] target/openrisc patches Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 01/24] target/openrisc: Rename the cpu from or32 to or1k Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 03/24] linux-user: Fix openrisc cpu_loop Richard Henderson
2017-02-13 21:25 ` Richard Henderson [this message]
2017-02-13 21:25 ` [Qemu-devel] [PULL 05/24] target/openrisc: Fix exception handling status registers Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 06/24] target/openrisc: Implement lwa, swa Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 07/24] target/openrisc: Tidy insn dumping Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 08/24] target/openrisc: Rationalize immediate extraction Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 09/24] target/openrisc: Streamline arithmetic and OVE Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 10/24] target/openrisc: Put SR[OVE] in TB flags Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 11/24] target/openrisc: Invert the decoding in dec_calc Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 12/24] target/openrisc: Keep SR_F in a separate variable Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 13/24] target/openrisc: Keep SR_CY and SR_OV in a separate variables Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 14/24] target/openrisc: Use movcond where appropriate Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 15/24] target/openrisc: Set flags on helpers Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 16/24] target/openrisc: Enable trap, csync, msync, psync for user mode Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 17/24] target/openrisc: Implement msync Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 18/24] target/openrisc: Represent MACHI:MACLO as a single unit Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 19/24] target/openrisc: Implement muld, muldu, macu, msbu Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 20/24] target/openrisc: Fix madd Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 21/24] target/openrisc: Optimize l.jal to next Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 22/24] target/openrisc: Tidy ppc/npc implementation Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 23/24] target/openrisc: Tidy handling of delayed branches Richard Henderson
2017-02-13 21:25 ` [Qemu-devel] [PULL 24/24] target/openrisc: Optimize for r0 being zero Richard Henderson
2017-02-14 11:01 ` [Qemu-devel] [PULL 00/24] target/openrisc patches Peter Maydell

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