From: Balbir Singh <bsingharora@gmail.com>
To: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au
Subject: Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition
Date: Mon, 20 Feb 2017 16:16:26 +1100 [thread overview]
Message-ID: <20170220051626.GA661@balbir.ozlabs.ibm.com> (raw)
In-Reply-To: <1487563478-22265-2-git-send-email-sjitindarsingh@gmail.com>
On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh wrote:
> POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
>
> Add a definition for this mmu model and set the POWER9 cpu model to use
> this mmu model.
>
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> ---
> target/ppc/cpu-qom.h | 5 ++++-
> target/ppc/mmu_helper.c | 2 ++
> target/ppc/translate_init.c | 3 +--
> 3 files changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index b7977ba..4e3132b 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -86,10 +86,13 @@ enum powerpc_mmu_t {
> POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> | POWERPC_MMU_64K
> | POWERPC_MMU_AMR | 0x00000004,
> - /* FIXME Add POWERPC_MMU_3_OO defines */
> /* Architecture 2.07 "degraded" (no 1T segments) */
> POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
> | 0x00000004,
> + /* Architecture 3.00 variant */
> + POWERPC_MMU_3_00 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> + | POWERPC_MMU_64K
> + | POWERPC_MMU_AMR | 0x00000005,
I wonder if we need a POWERPC_MMU_RADIX that we can then attach
with future versions
Balbir Singh.
next prev parent reply other threads:[~2017-02-20 5:16 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-20 4:04 [Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition Suraj Jitindar Singh
2017-02-20 5:16 ` Balbir Singh [this message]
2017-02-23 3:43 ` [Qemu-devel] [Qemu-ppc] " David Gibson
2017-02-23 4:21 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix LPCR DPFD mask define Suraj Jitindar Singh
2017-02-20 5:47 ` [Qemu-devel] [Qemu-ppc] " Balbir Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 Suraj Jitindar Singh
2017-02-20 7:31 ` [Qemu-devel] [Qemu-ppc] " Balbir Singh
2017-02-23 3:47 ` David Gibson
2017-02-23 4:21 ` Suraj Jitindar Singh
2017-02-23 3:45 ` [Qemu-devel] " David Gibson
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv Suraj Jitindar Singh
2017-02-21 4:22 ` Balbir Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState Suraj Jitindar Singh
2017-02-23 3:50 ` David Gibson
2017-02-23 4:22 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 06/10] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation Suraj Jitindar Singh
2017-02-23 3:57 ` David Gibson
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler Suraj Jitindar Singh
2017-02-23 4:08 ` David Gibson
2017-02-23 4:24 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 08/10] target/ppc/POWER9: Add POWER9 pa-features definition Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9 Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models Suraj Jitindar Singh
2017-02-23 4:09 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support David Gibson
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