From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44799) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1cfvEp-0001tu-Sw for qemu-devel@nongnu.org; Mon, 20 Feb 2017 16:11:30 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1cfvCc-0007L6-AZ for qemu-devel@nongnu.org; Mon, 20 Feb 2017 16:11:15 -0500 Received: from mx1.redhat.com ([209.132.183.28]:42182) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1cfvCc-0007Kj-37 for qemu-devel@nongnu.org; Mon, 20 Feb 2017 16:08:58 -0500 Date: Mon, 20 Feb 2017 14:08:56 -0700 From: Alex Williamson Message-ID: <20170220140856.2cd275e5@t450s.home> In-Reply-To: <1487554087-15347-4-git-send-email-tianyu.lan@intel.com> References: <1487554087-15347-1-git-send-email-tianyu.lan@intel.com> <1487554087-15347-4-git-send-email-tianyu.lan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [Resend RFC PATCH 3/4] Intel iommu: Add Intel IOMMU fault event callback List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Lan Tianyu Cc: qemu-devel@nongnu.org, kevin.tian@intel.com, mst@redhat.com, jan.kiszka@siemens.com, jasowang@redhat.com, peterx@redhat.com, david@gibson.dropbear.id.au, yi.l.liu@intel.com On Mon, 20 Feb 2017 09:28:06 +0800 Lan Tianyu wrote: > This patch is to deal with fault event reported from IOMMU driver. > > Signed-off-by: Lan Tianyu > --- > hw/i386/intel_iommu.c | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c > index 9b1ba1b..79507d2 100644 > --- a/hw/i386/intel_iommu.c > +++ b/hw/i386/intel_iommu.c > @@ -2286,6 +2286,30 @@ static void vtd_iommu_notify_flag_changed(MemoryRegion *iommu, > } > } > > +static void vtd_iommu_notify_fault_event(MemoryRegion *iommu, > + IOMMUFaultInfo *info) > +{ > + VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); > + IntelIOMMUState *s = vtd_as->iommu_state; > + bool is_fpd_set = false; > + uint8_t bus_num = pci_bus_num(vtd_as->bus); > + uint8_t devfn = vtd_as->devfn; > + VTDContextEntry ce; > + > + /* Replace source id with device's vbdf */ > + info->sid = vtd_make_source_id(bus_num, devfn); > + > + if (!vtd_dev_to_context_entry(s, bus_num, devfn, &ce)) { > + is_fpd_set = ce.lo & VTD_CONTEXT_ENTRY_FPD; > + if (is_fpd_set) { > + trace_vtd_fault_disabled(); > + } else { > + vtd_report_dmar_fault(s, info->sid, info->addr, > + info->fault_reason, info->is_write); Convenient that the error structure exactly matches the function parameters here. Is fault_reason going to be standardized across all IOMMU vendors? If not, how does QEMU know whether the type1 container is backed by VT-d, AMD-Vi, ARM SMMU, etc? > + } > + } > +} > + > static const VMStateDescription vtd_vmstate = { > .name = "iommu-intel", > .version_id = 1, > @@ -2816,6 +2840,7 @@ static void vtd_init(IntelIOMMUState *s) > > s->iommu_ops.translate = vtd_iommu_translate; > s->iommu_ops.notify_flag_changed = vtd_iommu_notify_flag_changed; > + s->iommu_ops.notify_fault_event = vtd_iommu_notify_fault_event; > s->iommu_ops.replay = vtd_iommu_replay; > s->root = 0; > s->root_extended = false;