From: Balbir Singh <bsingharora@gmail.com>
To: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, agraf@suse.de,
sam.bobroff@au1.ibm.com, david@gibson.dropbear.id.au
Subject: Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv
Date: Tue, 21 Feb 2017 15:22:05 +1100 [thread overview]
Message-ID: <20170221042205.GA23350@balbir.ozlabs.ibm.com> (raw)
In-Reply-To: <1487563478-22265-5-git-send-email-sjitindarsingh@gmail.com>
On Mon, Feb 20, 2017 at 03:04:32PM +1100, Suraj Jitindar Singh wrote:
> The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
> whether ISI and DSI interrupts were directed to the hypervisor or the
> partition. These interrupts now go to the hypervisor irrespective, thus
> it is no longer necessary to check the vmp0 bit in the LPCR.
>
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
Acked-by: Balbir Singh <bsingharora@gmail.com>
next prev parent reply other threads:[~2017-02-21 4:22 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-20 4:04 [Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition Suraj Jitindar Singh
2017-02-20 5:16 ` [Qemu-devel] [Qemu-ppc] " Balbir Singh
2017-02-23 3:43 ` David Gibson
2017-02-23 4:21 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix LPCR DPFD mask define Suraj Jitindar Singh
2017-02-20 5:47 ` [Qemu-devel] [Qemu-ppc] " Balbir Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9 Suraj Jitindar Singh
2017-02-20 7:31 ` [Qemu-devel] [Qemu-ppc] " Balbir Singh
2017-02-23 3:47 ` David Gibson
2017-02-23 4:21 ` Suraj Jitindar Singh
2017-02-23 3:45 ` [Qemu-devel] " David Gibson
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv Suraj Jitindar Singh
2017-02-21 4:22 ` Balbir Singh [this message]
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState Suraj Jitindar Singh
2017-02-23 3:50 ` David Gibson
2017-02-23 4:22 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 06/10] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation Suraj Jitindar Singh
2017-02-23 3:57 ` David Gibson
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler Suraj Jitindar Singh
2017-02-23 4:08 ` David Gibson
2017-02-23 4:24 ` Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 08/10] target/ppc/POWER9: Add POWER9 pa-features definition Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9 Suraj Jitindar Singh
2017-02-20 4:04 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models Suraj Jitindar Singh
2017-02-23 4:09 ` [Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support David Gibson
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