[Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support

[Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support

[Suraj Jitindar Singh]

This is V3 of the patch series to implement tcg emulation support for a
POWER9 cpu model for the pseries machine type running a legacy kernel.
That is a kernel which doesn't use the new radix mmu mode or the new hash
mmu mode with segment tables.

To use a POWER9 cpu provide the command line option "-cpu POWER9".

This series attempts to avoid precluding KVM-HV support for the POWER9
cpu model but doesn't attempt to support KVM-PR or the powernv machine
for the POWER9 cpu model as these aren't currently supported or
implemented and further code changes will be required in the event these
are implemented.

This series is used as a base to implement radix support.

The changes from V2 are as follows:

 - Only migrate the partition table entry on non-zero value
 - Change how register generation works to simplify adding/removing
   registers
 - Rename mmu.h -> mmu-book3s-v3.h
 - Error report and abort on attempt to use segment tables

Suraj Jitindar Singh (10):
  target/ppc/POWER9: Add ISAv3.00 MMU definition
  target/ppc: Fix LPCR DPFD mask define
  target/ppc/POWER9: Adapt LPCR handling for POWER9
  target/ppc/POWER9: Direct all instr and data storage interrupts to the
    hypv
  target/ppc: Add patb_entry to sPAPRMachineState
  target/ppc: Don't gen an SDR1 on POWER9 and rework register creation
  target/ppc/POWER9: Add POWER9 mmu fault handler
  target/ppc/POWER9: Add POWER9 pa-features definition
  target/ppc/POWER9: Add cpu_has_work function for POWER9
  hw/ppc/spapr: Add POWER9 to pseries cpu models

 hw/ppc/spapr.c              |  47 ++++++
 hw/ppc/spapr_cpu_core.c     |   3 +
 include/hw/ppc/spapr.h      |   1 +
 target/ppc/cpu-qom.h        |   5 +-
 target/ppc/cpu.h            |  21 ++-
 target/ppc/mmu-book3s-v3.h  |  50 ++++++
 target/ppc/mmu-hash64.c     |  53 +++++-
 target/ppc/mmu-hash64.h     |   4 +-
 target/ppc/mmu_helper.c     |  44 ++++-
 target/ppc/translate.c      |   7 +-
 target/ppc/translate_init.c | 391 ++++++++++++++++++++++++++++++--------------
 11 files changed, 485 insertions(+), 141 deletions(-)
 create mode 100644 target/ppc/mmu-book3s-v3.h

-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition

[Suraj Jitindar Singh]

POWER9 processors implement the mmu as defined in version 3.00 of the ISA.

Add a definition for this mmu model and set the POWER9 cpu model to use
this mmu model.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
---
 target/ppc/cpu-qom.h        | 5 ++++-
 target/ppc/mmu_helper.c     | 2 ++
 target/ppc/translate_init.c | 3 +--
 3 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
index b7977ba..4e3132b 100644
--- a/target/ppc/cpu-qom.h
+++ b/target/ppc/cpu-qom.h
@@ -86,10 +86,13 @@ enum powerpc_mmu_t {
     POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
                              | POWERPC_MMU_64K
                              | POWERPC_MMU_AMR | 0x00000004,
-    /* FIXME Add POWERPC_MMU_3_OO defines */
     /* Architecture 2.07 "degraded" (no 1T segments)           */
     POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
                              | 0x00000004,
+    /* Architecture 3.00 variant                               */
+    POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
+                             | POWERPC_MMU_64K
+                             | POWERPC_MMU_AMR | 0x00000005,
 };
 
 /*****************************************************************************/
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index f746f53..172a305 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1935,6 +1935,7 @@ void ppc_tlb_invalidate_all(CPUPPCState *env)
     case POWERPC_MMU_2_06a:
     case POWERPC_MMU_2_07:
     case POWERPC_MMU_2_07a:
+    case POWERPC_MMU_3_00:
 #endif /* defined(TARGET_PPC64) */
         env->tlb_need_flush = 0;
         tlb_flush(CPU(cpu));
@@ -1974,6 +1975,7 @@ void ppc_tlb_invalidate_one(CPUPPCState *env, target_ulong addr)
     case POWERPC_MMU_2_06a:
     case POWERPC_MMU_2_07:
     case POWERPC_MMU_2_07a:
+    case POWERPC_MMU_3_00:
         /* tlbie invalidate TLBs for all segments */
         /* XXX: given the fact that there are too many segments to invalidate,
          *      and we still don't have a tlb_flush_mask(env, n, mask) in QEMU,
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 76f79fa..84bf125 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8816,8 +8816,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
                     (1ull << MSR_PMM) |
                     (1ull << MSR_RI) |
                     (1ull << MSR_LE);
-    /* Using 2.07 defines until new radix model is added. */
-    pcc->mmu_model = POWERPC_MMU_2_07;
+    pcc->mmu_model = POWERPC_MMU_3_00;
 #if defined(CONFIG_SOFTMMU)
     pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
     /* segment page size remain the same */
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix LPCR DPFD mask define

[Suraj Jitindar Singh]

The DPFD field in the LPCR is 3 bits wide. This has always been defined
as 0x3 << shift which indicates a 2 bit field, which is incorrect.
Correct this.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
---
 target/ppc/cpu.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bc2a2ce..bb96dd5 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -381,7 +381,7 @@ struct ppc_slb_t {
 #define LPCR_ISL          (1ull << (63 - 2))
 #define LPCR_KBV          (1ull << (63 - 3))
 #define LPCR_DPFD_SHIFT   (63 - 11)
-#define LPCR_DPFD         (0x3ull << LPCR_DPFD_SHIFT)
+#define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 #define LPCR_VRMASD_SHIFT (63 - 16)
 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
 #define LPCR_RMLS_SHIFT   (63 - 37)
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9

[Suraj Jitindar Singh]

The logical partitioning control register controls a threads operation
based on the partition it is currently executing. Add new definitions and
update the mask used when writing to the LPCR based on the POWER9 spec.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
---
 target/ppc/cpu.h            | 18 ++++++++++++++++++
 target/ppc/mmu-hash64.c     |  8 ++++++++
 target/ppc/translate_init.c | 24 ++++++++++++++++++------
 3 files changed, 44 insertions(+), 6 deletions(-)

diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bb96dd5..425e79d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -384,12 +384,19 @@ struct ppc_slb_t {
 #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
 #define LPCR_VRMASD_SHIFT (63 - 16)
 #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
+/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
+#define LPCR_PECE_U_SHIFT (63 - 19)
+#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
+#define LPCR_HVEE         (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
 #define LPCR_RMLS_SHIFT   (63 - 37)
 #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
 #define LPCR_ILE          (1ull << (63 - 38))
 #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
 #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
+#define LPCR_UPRT         (1ull << (63 - 41)) /* Use Process Table */
+#define LPCR_EVIRT        (1ull << (63 - 42)) /* Enhanced Virtualisation */
 #define LPCR_ONL          (1ull << (63 - 45))
+#define LPCR_LD           (1ull << (63 - 46)) /* Large Decrementer */
 #define LPCR_P7_PECE0     (1ull << (63 - 49))
 #define LPCR_P7_PECE1     (1ull << (63 - 50))
 #define LPCR_P7_PECE2     (1ull << (63 - 51))
@@ -398,11 +405,22 @@ struct ppc_slb_t {
 #define LPCR_P8_PECE2     (1ull << (63 - 49))
 #define LPCR_P8_PECE3     (1ull << (63 - 50))
 #define LPCR_P8_PECE4     (1ull << (63 - 51))
+/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
+#define LPCR_PECE_L_SHIFT (63 - 51)
+#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
+#define LPCR_PDEE         (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
+#define LPCR_HDEE         (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
+#define LPCR_EEE          (1ull << (63 - 49)) /* External Exit Enable        */
+#define LPCR_DEE          (1ull << (63 - 50)) /* Decrementer Exit Enable     */
+#define LPCR_OEE          (1ull << (63 - 51)) /* Other Exit Enable           */
 #define LPCR_MER          (1ull << (63 - 52))
+#define LPCR_GTSE         (1ull << (63 - 53)) /* Guest Translation Shootdown */
 #define LPCR_TC           (1ull << (63 - 54))
+#define LPCR_HEIC         (1ull << (63 - 59)) /* HV Extern Interrupt Control */
 #define LPCR_LPES0        (1ull << (63 - 60))
 #define LPCR_LPES1        (1ull << (63 - 61))
 #define LPCR_RMI          (1ull << (63 - 62))
+#define LPCR_HVICE        (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
 #define LPCR_HDICE        (1ull << (63 - 63))
 
 #define msr_sf   ((env->msr >> MSR_SF)   & 1)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index bb78fb5..24d9901 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -1050,6 +1050,14 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
                       LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
                       LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
         break;
+    case POWERPC_MMU_3_00: /* P9 */
+        lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
+                      (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
+                      LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
+                      (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
+                      LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
+                      LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
+        break;
     default:
         ;
     }
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 84bf125..be35cbd 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8870,12 +8870,24 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
     lpcr->default_value &= ~LPCR_RMLS;
     lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
 
-    /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
-     * bit 47 and 48 which are reserved on P7. Here we set them all, which
-     * will work as expected for both implementations
-     */
-    lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
-                           LPCR_P8_PECE3 | LPCR_P8_PECE4;
+    switch (env->mmu_model) {
+    case POWERPC_MMU_3_00:
+        /* By default we choose legacy mode and switch to new hash or radix
+         * when a register process table hcall is made. So disable process
+         * tables and guest translation shootdown by default
+         */
+        lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
+        lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
+                               LPCR_OEE;
+        break;
+    default:
+        /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
+         * bit 47 and 48 which are reserved on P7. Here we set them all, which
+         * will work as expected for both implementations
+         */
+        lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
+                               LPCR_P8_PECE3 | LPCR_P8_PECE4;
+    }
 
     /* We should be followed by a CPU reset but update the active value
      * just in case...
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

[Suraj Jitindar Singh]

The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
whether ISI and DSI interrupts were directed to the hypervisor or the
partition. These interrupts now go to the hypervisor irrespective, thus
it is no longer necessary to check the vmp0 bit in the LPCR.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/mmu-hash64.c | 20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 24d9901..7c5d589 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -640,7 +640,15 @@ static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env,
     if (msr_ir) {
         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
     } else {
-        vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+        switch (env->mmu_model) {
+        case POWERPC_MMU_3_00:
+            /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+            vpm = true;
+            break;
+        default:
+            vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+            break;
+        }
     }
     if (vpm && !msr_hv) {
         cs->exception_index = POWERPC_EXCP_HISI;
@@ -658,7 +666,15 @@ static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64_t dar,
     if (msr_dr) {
         vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM1);
     } else {
-        vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+        switch (env->mmu_model) {
+        case POWERPC_MMU_3_00:
+            /* Field deprecated in ISAv3.00 - interrupts always go to hyperv */
+            vpm = true;
+            break;
+        default:
+            vpm = !!(env->spr[SPR_LPCR] & LPCR_VPM0);
+            break;
+        }
     }
     if (vpm && !msr_hv) {
         cs->exception_index = POWERPC_EXCP_HDSI;
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState

[Suraj Jitindar Singh]

ISA v3.00 adds the idea of a partition table which is used to store the
address translation details for all partitions on the system. The partition
table consists of double word entries indexed by partition id where the second
double word contains the location of the process table in guest memory. The
process table is registered by the guest via a h-call.

We need somewhere to store the address of the process table so we add an entry
to the sPAPRMachineState struct called patb_entry to represent the second
doubleword of a single partition table entry corresponding to the current
guest. We need to store this value so we know if the guest is using radix or
hash translation and the location of the corresponding process table in guest
memory. Since we only have a single guest per qemu instance, we only need one
entry.

Since the partition table is technically a hypervisor resource we require that
access to it is abstracted by the virtual hypervisor through the calls
[set/get]_patbe(). Currently the value of the entry is never set (and thus
defaults to 0 indicating hash), but it will be required to both implement
POWER9 kvm support and tcg radix support.

We also add this field to be migrated as part of the sPAPRMachineState as we
will need it on the receiving side as the guest will never tell us this
information again and we need it to perform translation.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>

---

V2->V3:
- Only add patbe to migration stream if non-zero
---
 hw/ppc/spapr.c         | 29 +++++++++++++++++++++++++++++
 include/hw/ppc/spapr.h |  1 +
 target/ppc/cpu.h       |  1 +
 3 files changed, 31 insertions(+)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e465d7a..2fbf193 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1018,6 +1018,13 @@ static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
     }
 }
 
+static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
+{
+    sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
+
+    return spapr->patb_entry;
+}
+
 #define HPTE(_table, _i)   (void *)(((uint64_t *)(_table)) + ((_i) * 2))
 #define HPTE_VALID(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
 #define HPTE_DIRTY(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
@@ -1141,6 +1148,8 @@ static void ppc_spapr_reset(void)
     /* Check for unknown sysbus devices */
     foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
 
+    spapr->patb_entry = 0;
+
     /* Allocate and/or reset the hash page table */
     spapr_reallocate_hpt(spapr,
                          spapr_hpt_shift_for_ramsize(machine->maxram_size),
@@ -1327,6 +1336,24 @@ static const VMStateDescription vmstate_spapr_ov5_cas = {
     },
 };
 
+static bool spapr_patb_entry_needed(void *opaque)
+{
+    sPAPRMachineState *spapr = opaque;
+
+    return !!spapr->patb_entry;
+}
+
+static const VMStateDescription vmstate_spapr_patb_entry = {
+    .name = "spapr_patb_entry",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .needed = spapr_patb_entry_needed,
+    .fields = (VMStateField[]) {
+        VMSTATE_UINT64(patb_entry, sPAPRMachineState),
+        VMSTATE_END_OF_LIST()
+    },
+};
+
 static const VMStateDescription vmstate_spapr = {
     .name = "spapr",
     .version_id = 3,
@@ -1344,6 +1371,7 @@ static const VMStateDescription vmstate_spapr = {
     },
     .subsections = (const VMStateDescription*[]) {
         &vmstate_spapr_ov5_cas,
+        &vmstate_spapr_patb_entry,
         NULL
     }
 };
@@ -2733,6 +2761,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
     nc->nmi_monitor_handler = spapr_nmi;
     smc->phb_placement = spapr_phb_placement;
     vhc->hypercall = emulate_spapr_hypercall;
+    vhc->get_patbe = spapr_get_patbe;
 }
 
 static const TypeInfo spapr_machine_info = {
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index a2d8964..c6a929a 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -63,6 +63,7 @@ struct sPAPRMachineState {
 
     void *htab;
     uint32_t htab_shift;
+    uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
     hwaddr rma_size;
     int vrma_adjust;
     ssize_t rtas_size;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 425e79d..684d632 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -1218,6 +1218,7 @@ struct PPCVirtualHypervisor {
 struct PPCVirtualHypervisorClass {
     InterfaceClass parent;
     void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
+    uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
 };
 
 #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 06/10] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation

[Suraj Jitindar Singh]

POWER9 doesn't have a storage description register 1 (SDR1) which is used
to store the base and size of the hash table. Thus we don't need to
generate this register on the POWER9 cpu model and thus shouldn't read or
write to it either. While we're here, init_proc_book3s_64 is a convoluted
mess which attempts to be a generic function which will then call cpu model
specific register gen functions, but we're calling it from a cpu model
specific function (pcc->init_proc) anyway. So instead of going from
cpu specific function -> generic function -> cpu specific functions, why
not just call the cpu specific register gen functions directly from the
cpu specific init_proc() function removing the need for init_proc_book3s_64
function altogether and hopefully clarifying the cpu model specific
register generation.

We rename ppc_hash64_set_sdr1->ppc_hash64_store_hpt to better represent
that the generic use of the function is to set the htab_[mask/base] and
sdr1 only if appropriate, and update call sites accordingly.

We update ppc_cpu_dump_state so that "info registers" will only display
the value of sdr1 if the register has been generated.

Finally, as mentioned above the register generation for the pcc->init_proc
function for 970, POWER5+, POWER7, POWER8 and POWER9 has been reworked
for improved clarity. Instead of calling init_proc_book3s_64 which then
attempts to generate the correct registers through a mess of if
statements, we remove this function and instead call the appropriate
register generation functions directly. This follows the register
generation model followed for earlier cpu models (pre-970) whereby cpu
specific registers are generated directly in the init_proc function
and makes it easier to add/remove specific registers for new cpu models.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>

---

V2->V3:
- Add rework of register generation
---
 target/ppc/mmu-hash64.c     |  17 ++-
 target/ppc/mmu-hash64.h     |   4 +-
 target/ppc/mmu_helper.c     |   2 +-
 target/ppc/translate.c      |   7 +-
 target/ppc/translate_init.c | 316 +++++++++++++++++++++++++++-----------------
 5 files changed, 218 insertions(+), 128 deletions(-)

diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 7c5d589..3e17a9f 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -285,13 +285,12 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 /*
  * 64-bit hash table MMU handling
  */
-void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
-                         Error **errp)
+void ppc_hash64_store_hpt(PowerPCCPU *cpu, target_ulong value,
+                          Error **errp)
 {
     CPUPPCState *env = &cpu->env;
     target_ulong htabsize = value & SDR_64_HTABSIZE;
 
-    env->spr[SPR_SDR1] = value;
     if (htabsize > 28) {
         error_setg(errp,
                    "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
@@ -300,6 +299,14 @@ void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
     }
     env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1;
     env->htab_base = value & SDR_64_HTABORG;
+
+    switch (env->mmu_model) {
+    case POWERPC_MMU_3_00:
+        break; /* Power 9 doesn't have an SDR1 */
+    default:
+        env->spr[SPR_SDR1] = value;
+        break;
+    }
 }
 
 void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
@@ -313,8 +320,8 @@ void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
     } else {
         env->external_htab = MMU_HASH64_KVM_MANAGED_HPT;
     }
-    ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
-                        &local_err);
+    ppc_hash64_store_hpt(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
+                         &local_err);
     if (local_err) {
         error_propagate(errp, local_err);
         return;
diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
index 7a0b7fc..2c00bce 100644
--- a/target/ppc/mmu-hash64.h
+++ b/target/ppc/mmu-hash64.h
@@ -91,8 +91,8 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
 #define HPTE64_V_1TB_SEG        0x4000000000000000ULL
 #define HPTE64_V_VRMA_MASK      0x4001ffffff000000ULL
 
-void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
-                         Error **errp);
+void ppc_hash64_store_hpt(PowerPCCPU *cpu, target_ulong value,
+                          Error **errp);
 void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
                                  Error **errp);
 
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 172a305..2911266 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -2005,7 +2005,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
         PowerPCCPU *cpu = ppc_env_get_cpu(env);
         Error *local_err = NULL;
 
-        ppc_hash64_set_sdr1(cpu, value, &local_err);
+        ppc_hash64_store_hpt(cpu, value, &local_err);
         if (local_err) {
             error_report_err(local_err);
             error_free(local_err);
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index b48abae..473a40a 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6850,9 +6850,12 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
     case POWERPC_MMU_2_06a:
     case POWERPC_MMU_2_07:
     case POWERPC_MMU_2_07a:
+    case POWERPC_MMU_3_00:
 #endif
-        cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "   DAR " TARGET_FMT_lx
-                       "  DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
+        if (env->spr_cb[SPR_SDR1].name) {
+            cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
+        }
+        cpu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",
                     env->spr[SPR_DAR], env->spr[SPR_DSISR]);
         break;
     case POWERPC_MMU_BOOKE206:
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index be35cbd..32c1619 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -723,7 +723,7 @@ static void gen_spr_generic (CPUPPCState *env)
 }
 
 /* SPR common to all non-embedded PowerPC, including 601 */
-static void gen_spr_ne_601 (CPUPPCState *env)
+static void gen_spr_ne_601(CPUPPCState *env)
 {
     /* Exception processing */
     spr_register_kvm(env, SPR_DSISR, "DSISR",
@@ -739,7 +739,11 @@ static void gen_spr_ne_601 (CPUPPCState *env)
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_decr, &spr_write_decr,
                  0x00000000);
-    /* Memory management */
+}
+
+/* Storage Description Register 1 */
+static void gen_spr_sdr1(CPUPPCState *env)
+{
     spr_register(env, SPR_SDR1, "SDR1",
                  SPR_NOACCESS, SPR_NOACCESS,
                  &spr_read_generic, &spr_write_sdr1,
@@ -1168,7 +1172,7 @@ static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
 }
 #endif /* CONFIG_USER_ONLY */
 
-static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
+static void gen_spr_amr(CPUPPCState *env)
 {
 #ifndef CONFIG_USER_ONLY
     /* Virtual Page Class Key protection */
@@ -1194,13 +1198,17 @@ static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
                     SPR_NOACCESS, SPR_NOACCESS,
                     &spr_read_generic, &spr_write_generic,
                     0);
-    if (has_iamr) {
-        spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
-                            SPR_NOACCESS, SPR_NOACCESS,
-                            &spr_read_generic, &spr_write_iamr,
-                            &spr_read_generic, &spr_write_generic,
-                            KVM_REG_PPC_IAMR, 0);
-    }
+#endif /* !CONFIG_USER_ONLY */
+}
+
+static void gen_spr_iamr(CPUPPCState *env)
+{
+#ifndef CONFIG_USER_ONLY
+    spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
+                        SPR_NOACCESS, SPR_NOACCESS,
+                        &spr_read_generic, &spr_write_iamr,
+                        &spr_read_generic, &spr_write_generic,
+                        KVM_REG_PPC_IAMR, 0);
 #endif /* !CONFIG_USER_ONLY */
 }
 #endif /* TARGET_PPC64 */
@@ -4410,6 +4418,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
 static void init_proc_G2 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_G2_755(env);
     gen_spr_G2(env);
     /* Time base */
@@ -4488,6 +4497,7 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
 static void init_proc_G2LE (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_G2_755(env);
     gen_spr_G2(env);
     /* Time base */
@@ -4723,6 +4733,7 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
 static void init_proc_e300 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_603(env);
     /* Time base */
     gen_tbl(env);
@@ -5222,6 +5233,7 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
 static void init_proc_601 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_601(env);
     /* Hardware implementation registers */
     /* XXX : not implemented */
@@ -5336,6 +5348,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
 static void init_proc_602 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_602(env);
     /* Time base */
     gen_tbl(env);
@@ -5405,6 +5418,7 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
 static void init_proc_603 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_603(env);
     /* Time base */
     gen_tbl(env);
@@ -5471,6 +5485,7 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
 static void init_proc_603E (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_603(env);
     /* Time base */
     gen_tbl(env);
@@ -5537,6 +5552,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
 static void init_proc_604 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_604(env);
     /* Time base */
     gen_tbl(env);
@@ -5600,6 +5616,7 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
 static void init_proc_604E (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_604(env);
     /* XXX : not implemented */
     spr_register(env, SPR_7XX_MMCR1, "MMCR1",
@@ -5683,6 +5700,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
 static void init_proc_740 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -5753,6 +5771,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
 static void init_proc_750 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* XXX : not implemented */
     spr_register(env, SPR_L2CR, "L2CR",
@@ -5831,6 +5850,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
 static void init_proc_750cl (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* XXX : not implemented */
     spr_register(env, SPR_L2CR, "L2CR",
@@ -6032,6 +6052,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
 static void init_proc_750cx (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* XXX : not implemented */
     spr_register(env, SPR_L2CR, "L2CR",
@@ -6114,6 +6135,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
 static void init_proc_750fx (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* XXX : not implemented */
     spr_register(env, SPR_L2CR, "L2CR",
@@ -6201,6 +6223,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
 static void init_proc_750gx (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* XXX : not implemented (XXX: different from 750fx) */
     spr_register(env, SPR_L2CR, "L2CR",
@@ -6288,6 +6311,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
 static void init_proc_745 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     gen_spr_G2_755(env);
     /* Time base */
@@ -6363,6 +6387,7 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
 static void init_proc_755 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     gen_spr_G2_755(env);
     /* Time base */
@@ -6449,6 +6474,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
 static void init_proc_7400 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -6527,6 +6553,7 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
 static void init_proc_7410 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -6611,6 +6638,7 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
 static void init_proc_7440 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -6718,6 +6746,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
 static void init_proc_7450 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -6851,6 +6880,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
 static void init_proc_7445 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -6987,6 +7017,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
 static void init_proc_7455 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -7125,6 +7156,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
 static void init_proc_7457 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -7287,6 +7319,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
 static void init_proc_e600 (CPUPPCState *env)
 {
     gen_spr_ne_601(env);
+    gen_spr_sdr1(env);
     gen_spr_7xx(env);
     /* Time base */
     gen_tbl(env);
@@ -7432,15 +7465,6 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
 #define POWERPC970_HID5_INIT 0x00000000
 #endif
 
-enum BOOK3S_CPU_TYPE {
-    BOOK3S_CPU_970,
-    BOOK3S_CPU_POWER5PLUS,
-    BOOK3S_CPU_POWER6,
-    BOOK3S_CPU_POWER7,
-    BOOK3S_CPU_POWER8,
-    BOOK3S_CPU_POWER9
-};
-
 static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
                                     int bit, int sprn, int cause)
 {
@@ -7528,7 +7552,7 @@ static void gen_spr_970_hior(CPUPPCState *env)
                  0x00000000);
 }
 
-static void gen_spr_book3s_common(CPUPPCState *env)
+static void gen_spr_book3s_ctrl(CPUPPCState *env)
 {
     spr_register(env, SPR_CTRL, "SPR_CTRL",
                  SPR_NOACCESS, SPR_NOACCESS,
@@ -8198,112 +8222,42 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
 #endif
 }
 
-static void init_proc_book3s_64(CPUPPCState *env, int version)
+static void init_proc_book3s_common(CPUPPCState *env)
 {
     gen_spr_ne_601(env);
     gen_tbl(env);
     gen_spr_book3s_altivec(env);
     gen_spr_book3s_pmu_sup(env);
     gen_spr_book3s_pmu_user(env);
-    gen_spr_book3s_common(env);
+    gen_spr_book3s_ctrl(env);
+}
 
-    switch (version) {
-    case BOOK3S_CPU_970:
-    case BOOK3S_CPU_POWER5PLUS:
-        gen_spr_970_hid(env);
-        gen_spr_970_hior(env);
-        gen_low_BATs(env);
-        gen_spr_970_pmu_sup(env);
-        gen_spr_970_pmu_user(env);
-        break;
-    case BOOK3S_CPU_POWER7:
-    case BOOK3S_CPU_POWER8:
-    case BOOK3S_CPU_POWER9:
-        gen_spr_book3s_ids(env);
-        gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
-        gen_spr_book3s_purr(env);
-        env->ci_large_pages = true;
-        break;
-    default:
-        g_assert_not_reached();
-    }
-    if (version >= BOOK3S_CPU_POWER5PLUS) {
-        gen_spr_power5p_common(env);
-        gen_spr_power5p_lpar(env);
-        gen_spr_power5p_ear(env);
-    } else {
-        gen_spr_970_lpar(env);
-    }
-    if (version == BOOK3S_CPU_970) {
-        gen_spr_970_dbg(env);
-    }
-    if (version >= BOOK3S_CPU_POWER6) {
-        gen_spr_power6_common(env);
-        gen_spr_power6_dbg(env);
-    }
-    if (version == BOOK3S_CPU_POWER7) {
-        gen_spr_power7_book4(env);
-    }
-    if (version >= BOOK3S_CPU_POWER8) {
-        gen_spr_power8_tce_address_control(env);
-        gen_spr_power8_ids(env);
-        gen_spr_power8_ebb(env);
-        gen_spr_power8_fscr(env);
-        gen_spr_power8_pmu_sup(env);
-        gen_spr_power8_pmu_user(env);
-        gen_spr_power8_tm(env);
-        gen_spr_power8_pspb(env);
-        gen_spr_vtb(env);
-        gen_spr_power8_ic(env);
-        gen_spr_power8_book4(env);
-        gen_spr_power8_rpr(env);
-    }
-    if (version < BOOK3S_CPU_POWER8) {
-        gen_spr_book3s_dbg(env);
-    } else {
-        gen_spr_book3s_207_dbg(env);
-    }
+static void init_proc_970(CPUPPCState *env)
+{
+    /* Common Registers */
+    init_proc_book3s_common(env);
+    gen_spr_sdr1(env);
+    gen_spr_book3s_dbg(env);
+
+    /* 970 Specific Registers */
+    gen_spr_970_hid(env);
+    gen_spr_970_hior(env);
+    gen_low_BATs(env);
+    gen_spr_970_pmu_sup(env);
+    gen_spr_970_pmu_user(env);
+    gen_spr_970_lpar(env);
+    gen_spr_970_dbg(env);
+
+    /* env variables */
 #if !defined(CONFIG_USER_ONLY)
-    switch (version) {
-    case BOOK3S_CPU_970:
-    case BOOK3S_CPU_POWER5PLUS:
-        env->slb_nr = 64;
-        break;
-    case BOOK3S_CPU_POWER7:
-    case BOOK3S_CPU_POWER8:
-    case BOOK3S_CPU_POWER9:
-    default:
-        env->slb_nr = 32;
-        break;
-    }
+    env->slb_nr = 64;
 #endif
-    /* Allocate hardware IRQ controller */
-    switch (version) {
-    case BOOK3S_CPU_970:
-    case BOOK3S_CPU_POWER5PLUS:
-        init_excp_970(env);
-        ppc970_irq_init(ppc_env_get_cpu(env));
-        break;
-    case BOOK3S_CPU_POWER7:
-        init_excp_POWER7(env);
-        ppcPOWER7_irq_init(ppc_env_get_cpu(env));
-        break;
-    case BOOK3S_CPU_POWER8:
-    case BOOK3S_CPU_POWER9:
-        init_excp_POWER8(env);
-        ppcPOWER7_irq_init(ppc_env_get_cpu(env));
-        break;
-    default:
-        g_assert_not_reached();
-    }
-
     env->dcache_line_size = 128;
     env->icache_line_size = 128;
-}
 
-static void init_proc_970(CPUPPCState *env)
-{
-    init_proc_book3s_64(env, BOOK3S_CPU_970);
+    /* Allocate hardware IRQ controller */
+    init_excp_970(env);
+    ppc970_irq_init(ppc_env_get_cpu(env));
 }
 
 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
@@ -8355,7 +8309,31 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
 
 static void init_proc_power5plus(CPUPPCState *env)
 {
-    init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
+    /* Common Registers */
+    init_proc_book3s_common(env);
+    gen_spr_sdr1(env);
+    gen_spr_book3s_dbg(env);
+
+    /* POWER5+ Specific Registers */
+    gen_spr_970_hid(env);
+    gen_spr_970_hior(env);
+    gen_low_BATs(env);
+    gen_spr_970_pmu_sup(env);
+    gen_spr_970_pmu_user(env);
+    gen_spr_power5p_common(env);
+    gen_spr_power5p_lpar(env);
+    gen_spr_power5p_ear(env);
+
+    /* env variables */
+#if !defined(CONFIG_USER_ONLY)
+    env->slb_nr = 64;
+#endif
+    env->dcache_line_size = 128;
+    env->icache_line_size = 128;
+
+    /* Allocate hardware IRQ controller */
+    init_excp_970(env);
+    ppc970_irq_init(ppc_env_get_cpu(env));
 }
 
 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
@@ -8508,7 +8486,33 @@ static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
 
 static void init_proc_POWER7 (CPUPPCState *env)
 {
-    init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
+    /* Common Registers */
+    init_proc_book3s_common(env);
+    gen_spr_sdr1(env);
+    gen_spr_book3s_dbg(env);
+
+    /* POWER7 Specific Registers */
+    gen_spr_book3s_ids(env);
+    gen_spr_amr(env);
+    gen_spr_book3s_purr(env);
+    gen_spr_power5p_common(env);
+    gen_spr_power5p_lpar(env);
+    gen_spr_power5p_ear(env);
+    gen_spr_power6_common(env);
+    gen_spr_power6_dbg(env);
+    gen_spr_power7_book4(env);
+
+    /* env variables */
+#if !defined(CONFIG_USER_ONLY)
+    env->slb_nr = 32;
+#endif
+    env->ci_large_pages = true;
+    env->dcache_line_size = 128;
+    env->icache_line_size = 128;
+
+    /* Allocate hardware IRQ controller */
+    init_excp_POWER7(env);
+    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
 }
 
 static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -8624,7 +8628,45 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
 
 static void init_proc_POWER8(CPUPPCState *env)
 {
-    init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
+    /* Common Registers */
+    init_proc_book3s_common(env);
+    gen_spr_sdr1(env);
+    gen_spr_book3s_207_dbg(env);
+
+    /* POWER8 Specific Registers */
+    gen_spr_book3s_ids(env);
+    gen_spr_amr(env);
+    gen_spr_iamr(env);
+    gen_spr_book3s_purr(env);
+    gen_spr_power5p_common(env);
+    gen_spr_power5p_lpar(env);
+    gen_spr_power5p_ear(env);
+    gen_spr_power6_common(env);
+    gen_spr_power6_dbg(env);
+    gen_spr_power8_tce_address_control(env);
+    gen_spr_power8_ids(env);
+    gen_spr_power8_ebb(env);
+    gen_spr_power8_fscr(env);
+    gen_spr_power8_pmu_sup(env);
+    gen_spr_power8_pmu_user(env);
+    gen_spr_power8_tm(env);
+    gen_spr_power8_pspb(env);
+    gen_spr_vtb(env);
+    gen_spr_power8_ic(env);
+    gen_spr_power8_book4(env);
+    gen_spr_power8_rpr(env);
+
+    /* env variables */
+#if !defined(CONFIG_USER_ONLY)
+    env->slb_nr = 32;
+#endif
+    env->ci_large_pages = true;
+    env->dcache_line_size = 128;
+    env->icache_line_size = 128;
+
+    /* Allocate hardware IRQ controller */
+    init_excp_POWER8(env);
+    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
 }
 
 static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
@@ -8752,9 +8794,47 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
     pcc->l1_icache_size = 0x8000;
     pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
 }
+
 static void init_proc_POWER9(CPUPPCState *env)
 {
-    init_proc_book3s_64(env, BOOK3S_CPU_POWER9);
+    /* Common Registers */
+    init_proc_book3s_common(env);
+    gen_spr_book3s_207_dbg(env);
+
+    /* POWER8 Specific Registers */
+    gen_spr_book3s_ids(env);
+    gen_spr_amr(env);
+    gen_spr_iamr(env);
+    gen_spr_book3s_purr(env);
+    gen_spr_power5p_common(env);
+    gen_spr_power5p_lpar(env);
+    gen_spr_power5p_ear(env);
+    gen_spr_power6_common(env);
+    gen_spr_power6_dbg(env);
+    gen_spr_power8_tce_address_control(env);
+    gen_spr_power8_ids(env);
+    gen_spr_power8_ebb(env);
+    gen_spr_power8_fscr(env);
+    gen_spr_power8_pmu_sup(env);
+    gen_spr_power8_pmu_user(env);
+    gen_spr_power8_tm(env);
+    gen_spr_power8_pspb(env);
+    gen_spr_vtb(env);
+    gen_spr_power8_ic(env);
+    gen_spr_power8_book4(env);
+    gen_spr_power8_rpr(env);
+
+    /* env variables */
+#if !defined(CONFIG_USER_ONLY)
+    env->slb_nr = 32;
+#endif
+    env->ci_large_pages = true;
+    env->dcache_line_size = 128;
+    env->icache_line_size = 128;
+
+    /* Allocate hardware IRQ controller */
+    init_excp_POWER8(env);
+    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
 }
 
 static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler

[Suraj Jitindar Singh]

Add a new mmu fault handler for the POWER9 cpu and add it as the handler
for the POWER9 cpu definition.

This handler checks if the guest is radix or hash based on the value in the
partition table entry and calls the correct fault handler accordingly.

The hash fault handling code has also been updated to check if the
partition is using segment tables.

Currently only legacy hash (no segment tables) is supported.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>

---

V2->V3:
- error_report on attempt to use segment tables instead of just LOG()
- Rename mmu.h -> mmu-book3s-v3.h
---
 target/ppc/mmu-book3s-v3.h  | 50 +++++++++++++++++++++++++++++++++++++++++++++
 target/ppc/mmu-hash64.c     |  8 ++++++++
 target/ppc/mmu_helper.c     | 40 ++++++++++++++++++++++++++++++++++++
 target/ppc/translate_init.c |  3 ++-
 4 files changed, 100 insertions(+), 1 deletion(-)
 create mode 100644 target/ppc/mmu-book3s-v3.h

diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
new file mode 100644
index 0000000..9375921
--- /dev/null
+++ b/target/ppc/mmu-book3s-v3.h
@@ -0,0 +1,50 @@
+/*
+ *  PowerPC emulation generic mmu definitions for qemu.
+ *
+ *  Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef MMU_H
+#define MMU_H
+
+#ifndef CONFIG_USER_ONLY
+
+/* Partition Table Entry Fields */
+#define PATBE1_GR 0x8000000000000000
+
+#ifdef TARGET_PPC64
+
+static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
+{
+    return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
+}
+
+static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
+{
+    PPCVirtualHypervisorClass *vhc =
+        PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
+
+    return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
+}
+
+int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
+                              int mmu_idx);
+
+#endif /* TARGET_PPC64 */
+
+#endif /* CONFIG_USER_ONLY */
+
+#endif /* MMU_H */
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index 3e17a9f..a581b50 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -27,6 +27,7 @@
 #include "kvm_ppc.h"
 #include "mmu-hash64.h"
 #include "exec/log.h"
+#include "mmu-book3s-v3.h"
 
 //#define DEBUG_SLB
 
@@ -767,6 +768,13 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
     /* 2. Translation is on, so look up the SLB */
     slb = slb_lookup(cpu, eaddr);
     if (!slb) {
+        /* No entry found, check if in-memory segment tables are in use */
+        if (ppc64_use_proc_tbl(cpu)) {
+            /* TODO - Unsupported */
+            error_report("Segment Table Support Unimplemented");
+            abort();
+        }
+        /* Segment still not found, generate the appropriate interrupt */
         if (rwx == 2) {
             cs->exception_index = POWERPC_EXCP_ISEG;
             env->error_code = 0;
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 2911266..527123c 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -28,6 +28,8 @@
 #include "exec/cpu_ldst.h"
 #include "exec/log.h"
 #include "helper_regs.h"
+#include "qemu/error-report.h"
+#include "mmu-book3s-v3.h"
 
 //#define DEBUG_MMU
 //#define DEBUG_BATS
@@ -1280,6 +1282,17 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
     case POWERPC_MMU_2_07a:
         dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
         break;
+    case POWERPC_MMU_3_00:
+        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
+            /* TODO - Unsupported */
+        } else {
+            if (ppc64_use_proc_tbl(ppc_env_get_cpu(env))) {
+                /* TODO - Unsupported */
+            } else {
+                dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
+                break;
+            }
+        }
 #endif
     default:
         qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__);
@@ -1421,6 +1434,17 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     case POWERPC_MMU_2_07:
     case POWERPC_MMU_2_07a:
         return ppc_hash64_get_phys_page_debug(cpu, addr);
+    case POWERPC_MMU_3_00:
+        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
+            /* TODO - Unsupported */
+        } else {
+            if (ppc64_use_proc_tbl(ppc_env_get_cpu(env))) {
+                /* TODO - Unsupported */
+            } else {
+                return ppc_hash64_get_phys_page_debug(cpu, addr);
+            }
+        }
+        break;
 #endif
 
     case POWERPC_MMU_32B:
@@ -2907,3 +2931,19 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
                                retaddr);
     }
 }
+
+/******************************************************************************/
+
+/* ISA v3.00 (POWER9) Generic MMU Helpers */
+
+int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
+                              int mmu_idx)
+{
+    if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
+        /* TODO - Unsupported */
+        error_report("Guest Radix Support Unimplemented");
+        abort();
+    } else { /* Guest uses hash */
+        return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
+    }
+}
diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 32c1619..7661c21 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -32,6 +32,7 @@
 #include "qapi/visitor.h"
 #include "hw/qdev-properties.h"
 #include "hw/ppc/ppc.h"
+#include "mmu-book3s-v3.h"
 
 //#define PPC_DUMP_CPU
 //#define PPC_DEBUG_SPR
@@ -8898,7 +8899,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
                     (1ull << MSR_LE);
     pcc->mmu_model = POWERPC_MMU_3_00;
 #if defined(CONFIG_SOFTMMU)
-    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
+    pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
     /* segment page size remain the same */
     pcc->sps = &POWER7_POWER8_sps;
 #endif
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 08/10] target/ppc/POWER9: Add POWER9 pa-features definition

[Suraj Jitindar Singh]

Add a pa-features definition which includes all of the new fields which
have been added, note we don't claim support for any of these new features
at this stage.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/spapr.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 2fbf193..cef950d 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -356,6 +356,20 @@ static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
         0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
         0x00, 0x00, 0x00, 0x00, 0x80, 0x00,
         0x80, 0x00, 0x80, 0x00, 0x00, 0x00 };
+    /* Currently we don't advertise any of the "new" ISAv3.00 functionality */
+    uint8_t pa_features_300[] = { 64, 0,
+        0xf6, 0x1f, 0xc7, 0xc0, 0x80, 0xf0, /*  0 -  5 */
+        0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /*  6 - 11 */
+        0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */
+        0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 24 - 29 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 - 35 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 36 - 41 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 42 - 47 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 48 - 53 */
+        0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 54 - 59 */
+        0x00, 0x00, 0x00, 0x00           }; /* 60 - 63 */
+
     uint8_t *pa_features;
     size_t pa_size;
 
@@ -370,6 +384,10 @@ static void spapr_populate_pa_features(CPUPPCState *env, void *fdt, int offset)
         pa_features = pa_features_207;
         pa_size = sizeof(pa_features_207);
         break;
+    case POWERPC_MMU_3_00:
+        pa_features = pa_features_300;
+        pa_size = sizeof(pa_features_300);
+        break;
     default:
         return;
     }
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 09/10] target/ppc/POWER9: Add cpu_has_work function for POWER9

[Suraj Jitindar Singh]

The cpu has work function is used to mask interrupts used to determine
if there is work for the cpu based on the LPCR. Add a function to do this
for POWER9 and add it to the POWER9 cpu definition. This is similar to that
for POWER8 except using the LPCR bits as defined for POWER9.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 target/ppc/translate_init.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 45 insertions(+)

diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
index 7661c21..840d62e 100644
--- a/target/ppc/translate_init.c
+++ b/target/ppc/translate_init.c
@@ -8846,10 +8846,54 @@ static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)
     return false;
 }
 
+static bool cpu_has_work_POWER9(CPUState *cs)
+{
+    PowerPCCPU *cpu = POWERPC_CPU(cs);
+    CPUPPCState *env = &cpu->env;
+
+    if (cs->halted) {
+        if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) {
+            return false;
+        }
+        /* External Exception */
+        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
+            (env->spr[SPR_LPCR] & LPCR_EEE)) {
+            return true;
+        }
+        /* Decrementer Exception */
+        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DECR)) &&
+            (env->spr[SPR_LPCR] & LPCR_DEE)) {
+            return true;
+        }
+        /* Machine Check or Hypervisor Maintenance Exception */
+        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_MCK |
+            1u << PPC_INTERRUPT_HMI)) && (env->spr[SPR_LPCR] & LPCR_OEE)) {
+            return true;
+        }
+        /* Privileged Doorbell Exception */
+        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_DOORBELL)) &&
+            (env->spr[SPR_LPCR] & LPCR_PDEE)) {
+            return true;
+        }
+        /* Hypervisor Doorbell Exception */
+        if ((env->pending_interrupts & (1u << PPC_INTERRUPT_HDOORBELL)) &&
+            (env->spr[SPR_LPCR] & LPCR_HDEE)) {
+            return true;
+        }
+        if (env->pending_interrupts & (1u << PPC_INTERRUPT_RESET)) {
+            return true;
+        }
+        return false;
+    } else {
+        return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+    }
+}
+
 POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
     PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
+    CPUClass *cc = CPU_CLASS(oc);
 
     dc->fw_name = "PowerPC,POWER9";
     dc->desc = "POWER9";
@@ -8860,6 +8904,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
                          PCR_COMPAT_2_05;
     pcc->init_proc = init_proc_POWER9;
     pcc->check_pow = check_pow_nocheck;
+    cc->has_work = cpu_has_work_POWER9;
     pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
                        PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
                        PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
-- 
2.5.5

[Qemu-devel] [QEMU-PPC] [PATCH V3 10/10] hw/ppc/spapr: Add POWER9 to pseries cpu models

[Suraj Jitindar Singh]

Add POWER9 cpu to list of spapr core models which allows it to be specified
as the cpu model for a pseries guest (e.g. -machine pseries -cpu POWER9).

This now allows a POWER9 cpu to boot to userspace in tcg emulation for a
pseries machine with a legacy kernel.

Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
---
 hw/ppc/spapr_cpu_core.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 9dddaeb..71253f9 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -360,6 +360,9 @@ static const char *spapr_core_models[] = {
 
     /* POWER8NVL */
     "POWER8NVL_v1.0",
+
+    /* POWER9 */
+    "POWER9_v1.0",
 };
 
 void spapr_cpu_core_class_init(ObjectClass *oc, void *data)
-- 
2.5.5

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition

[Balbir Singh]

On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh wrote:
> POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
> 
> Add a definition for this mmu model and set the POWER9 cpu model to use
> this mmu model.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> ---
>  target/ppc/cpu-qom.h        | 5 ++++-
>  target/ppc/mmu_helper.c     | 2 ++
>  target/ppc/translate_init.c | 3 +--
>  3 files changed, 7 insertions(+), 3 deletions(-)
> 
> diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> index b7977ba..4e3132b 100644
> --- a/target/ppc/cpu-qom.h
> +++ b/target/ppc/cpu-qom.h
> @@ -86,10 +86,13 @@ enum powerpc_mmu_t {
>      POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
>                               | POWERPC_MMU_64K
>                               | POWERPC_MMU_AMR | 0x00000004,
> -    /* FIXME Add POWERPC_MMU_3_OO defines */
>      /* Architecture 2.07 "degraded" (no 1T segments)           */
>      POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
>                               | 0x00000004,
> +    /* Architecture 3.00 variant                               */
> +    POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> +                             | POWERPC_MMU_64K
> +                             | POWERPC_MMU_AMR | 0x00000005,

I wonder if we need a POWERPC_MMU_RADIX that we can then attach
with future versions

Balbir Singh.

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 02/10] target/ppc: Fix LPCR DPFD mask define

[Balbir Singh]

On Mon, Feb 20, 2017 at 03:04:30PM +1100, Suraj Jitindar Singh wrote:
> The DPFD field in the LPCR is 3 bits wide. This has always been defined
> as 0x3 << shift which indicates a 2 bit field, which is incorrect.
> Correct this.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> ---

Acked-by: Balbir Singh <bsingharora@gmail.com>

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9

[Balbir Singh]

On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh wrote:
> The logical partitioning control register controls a threads operation
> based on the partition it is currently executing. Add new definitions and
> update the mask used when writing to the LPCR based on the POWER9 spec.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> ---
>  target/ppc/cpu.h            | 18 ++++++++++++++++++
>  target/ppc/mmu-hash64.c     |  8 ++++++++
>  target/ppc/translate_init.c | 24 ++++++++++++++++++------
>  3 files changed, 44 insertions(+), 6 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index bb96dd5..425e79d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -384,12 +384,19 @@ struct ppc_slb_t {
>  #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
>  #define LPCR_VRMASD_SHIFT (63 - 16)
>  #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
> +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
> +#define LPCR_PECE_U_SHIFT (63 - 19)
> +#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
> +#define LPCR_HVEE         (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
>  #define LPCR_RMLS_SHIFT   (63 - 37)
>  #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
>  #define LPCR_ILE          (1ull << (63 - 38))
>  #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
>  #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
> +#define LPCR_UPRT         (1ull << (63 - 41)) /* Use Process Table */
> +#define LPCR_EVIRT        (1ull << (63 - 42)) /* Enhanced Virtualisation */
>  #define LPCR_ONL          (1ull << (63 - 45))
> +#define LPCR_LD           (1ull << (63 - 46)) /* Large Decrementer */
>  #define LPCR_P7_PECE0     (1ull << (63 - 49))
>  #define LPCR_P7_PECE1     (1ull << (63 - 50))
>  #define LPCR_P7_PECE2     (1ull << (63 - 51))
> @@ -398,11 +405,22 @@ struct ppc_slb_t {
>  #define LPCR_P8_PECE2     (1ull << (63 - 49))
>  #define LPCR_P8_PECE3     (1ull << (63 - 50))
>  #define LPCR_P8_PECE4     (1ull << (63 - 51))
> +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
> +#define LPCR_PECE_L_SHIFT (63 - 51)
> +#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
> +#define LPCR_PDEE         (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
> +#define LPCR_HDEE         (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
> +#define LPCR_EEE          (1ull << (63 - 49)) /* External Exit Enable        */
> +#define LPCR_DEE          (1ull << (63 - 50)) /* Decrementer Exit Enable     */
> +#define LPCR_OEE          (1ull << (63 - 51)) /* Other Exit Enable           */
>  #define LPCR_MER          (1ull << (63 - 52))
> +#define LPCR_GTSE         (1ull << (63 - 53)) /* Guest Translation Shootdown */
>  #define LPCR_TC           (1ull << (63 - 54))
> +#define LPCR_HEIC         (1ull << (63 - 59)) /* HV Extern Interrupt Control */
>  #define LPCR_LPES0        (1ull << (63 - 60))
>  #define LPCR_LPES1        (1ull << (63 - 61))
>  #define LPCR_RMI          (1ull << (63 - 62))
> +#define LPCR_HVICE        (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
>  #define LPCR_HDICE        (1ull << (63 - 63))

This patch is missing

#define LPCR_HR	(1ull << (63 - 43))	/* HV uses Radix Tree Translation */

See arch/powerpc/include/asm/reg.h in the Linux kernel. 

Balbir Singh.

Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 04/10] target/ppc/POWER9: Direct all instr and data storage interrupts to the hypv

[Balbir Singh]

On Mon, Feb 20, 2017 at 03:04:32PM +1100, Suraj Jitindar Singh wrote:
> The vpm0 bit was removed from the LPCR in POWER9, this bit controlled
> whether ISI and DSI interrupts were directed to the hypervisor or the
> partition. These interrupts now go to the hypervisor irrespective, thus
> it is no longer necessary to check the vmp0 bit in the LPCR.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---

Acked-by: Balbir Singh <bsingharora@gmail.com>

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition

[David Gibson]

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On Mon, Feb 20, 2017 at 04:16:26PM +1100, Balbir Singh wrote:
> On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh wrote:
> > POWER9 processors implement the mmu as defined in version 3.00 of the ISA.
> > 
> > Add a definition for this mmu model and set the POWER9 cpu model to use
> > this mmu model.
> > 
> > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> > ---
> >  target/ppc/cpu-qom.h        | 5 ++++-
> >  target/ppc/mmu_helper.c     | 2 ++
> >  target/ppc/translate_init.c | 3 +--
> >  3 files changed, 7 insertions(+), 3 deletions(-)
> > 
> > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> > index b7977ba..4e3132b 100644
> > --- a/target/ppc/cpu-qom.h
> > +++ b/target/ppc/cpu-qom.h
> > @@ -86,10 +86,13 @@ enum powerpc_mmu_t {
> >      POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> >                               | POWERPC_MMU_64K
> >                               | POWERPC_MMU_AMR | 0x00000004,
> > -    /* FIXME Add POWERPC_MMU_3_OO defines */
> >      /* Architecture 2.07 "degraded" (no 1T segments)           */
> >      POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
> >                               | 0x00000004,
> > +    /* Architecture 3.00 variant                               */
> > +    POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > +                             | POWERPC_MMU_64K
> > +                             | POWERPC_MMU_AMR | 0x00000005,
> 
> I wonder if we need a POWERPC_MMU_RADIX that we can then attach
> with future versions

That's probably a good idea.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9

[David Gibson]

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On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh wrote:
> The logical partitioning control register controls a threads operation
> based on the partition it is currently executing. Add new definitions and
> update the mask used when writing to the LPCR based on the POWER9 spec.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>

> ---
>  target/ppc/cpu.h            | 18 ++++++++++++++++++
>  target/ppc/mmu-hash64.c     |  8 ++++++++
>  target/ppc/translate_init.c | 24 ++++++++++++++++++------
>  3 files changed, 44 insertions(+), 6 deletions(-)
> 
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index bb96dd5..425e79d 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -384,12 +384,19 @@ struct ppc_slb_t {
>  #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
>  #define LPCR_VRMASD_SHIFT (63 - 16)
>  #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
> +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
> +#define LPCR_PECE_U_SHIFT (63 - 19)
> +#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
> +#define LPCR_HVEE         (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
>  #define LPCR_RMLS_SHIFT   (63 - 37)
>  #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
>  #define LPCR_ILE          (1ull << (63 - 38))
>  #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
>  #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
> +#define LPCR_UPRT         (1ull << (63 - 41)) /* Use Process Table */
> +#define LPCR_EVIRT        (1ull << (63 - 42)) /* Enhanced Virtualisation */
>  #define LPCR_ONL          (1ull << (63 - 45))
> +#define LPCR_LD           (1ull << (63 - 46)) /* Large Decrementer */
>  #define LPCR_P7_PECE0     (1ull << (63 - 49))
>  #define LPCR_P7_PECE1     (1ull << (63 - 50))
>  #define LPCR_P7_PECE2     (1ull << (63 - 51))
> @@ -398,11 +405,22 @@ struct ppc_slb_t {
>  #define LPCR_P8_PECE2     (1ull << (63 - 49))
>  #define LPCR_P8_PECE3     (1ull << (63 - 50))
>  #define LPCR_P8_PECE4     (1ull << (63 - 51))
> +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
> +#define LPCR_PECE_L_SHIFT (63 - 51)
> +#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
> +#define LPCR_PDEE         (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
> +#define LPCR_HDEE         (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
> +#define LPCR_EEE          (1ull << (63 - 49)) /* External Exit Enable        */
> +#define LPCR_DEE          (1ull << (63 - 50)) /* Decrementer Exit Enable     */
> +#define LPCR_OEE          (1ull << (63 - 51)) /* Other Exit Enable           */
>  #define LPCR_MER          (1ull << (63 - 52))
> +#define LPCR_GTSE         (1ull << (63 - 53)) /* Guest Translation Shootdown */
>  #define LPCR_TC           (1ull << (63 - 54))
> +#define LPCR_HEIC         (1ull << (63 - 59)) /* HV Extern Interrupt Control */
>  #define LPCR_LPES0        (1ull << (63 - 60))
>  #define LPCR_LPES1        (1ull << (63 - 61))
>  #define LPCR_RMI          (1ull << (63 - 62))
> +#define LPCR_HVICE        (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
>  #define LPCR_HDICE        (1ull << (63 - 63))
>  
>  #define msr_sf   ((env->msr >> MSR_SF)   & 1)
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index bb78fb5..24d9901 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -1050,6 +1050,14 @@ void helper_store_lpcr(CPUPPCState *env, target_ulong val)
>                        LPCR_P8_PECE2 | LPCR_P8_PECE3 | LPCR_P8_PECE4 |
>                        LPCR_MER | LPCR_TC | LPCR_LPES0 | LPCR_HDICE);
>          break;
> +    case POWERPC_MMU_3_00: /* P9 */
> +        lpcr = val & (LPCR_VPM1 | LPCR_ISL | LPCR_KBV | LPCR_DPFD |
> +                      (LPCR_PECE_U_MASK & LPCR_HVEE) | LPCR_ILE | LPCR_AIL |
> +                      LPCR_UPRT | LPCR_EVIRT | LPCR_ONL |
> +                      (LPCR_PECE_L_MASK & (LPCR_PDEE | LPCR_HDEE | LPCR_EEE |
> +                      LPCR_DEE | LPCR_OEE)) | LPCR_MER | LPCR_GTSE | LPCR_TC |
> +                      LPCR_HEIC | LPCR_LPES0 | LPCR_HVICE | LPCR_HDICE);
> +        break;
>      default:
>          ;
>      }
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 84bf125..be35cbd 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -8870,12 +8870,24 @@ void cpu_ppc_set_papr(PowerPCCPU *cpu)
>      lpcr->default_value &= ~LPCR_RMLS;
>      lpcr->default_value |= 1ull << LPCR_RMLS_SHIFT;
>  
> -    /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
> -     * bit 47 and 48 which are reserved on P7. Here we set them all, which
> -     * will work as expected for both implementations
> -     */
> -    lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
> -                           LPCR_P8_PECE3 | LPCR_P8_PECE4;
> +    switch (env->mmu_model) {
> +    case POWERPC_MMU_3_00:
> +        /* By default we choose legacy mode and switch to new hash or radix
> +         * when a register process table hcall is made. So disable process
> +         * tables and guest translation shootdown by default
> +         */
> +        lpcr->default_value &= ~(LPCR_UPRT | LPCR_GTSE);
> +        lpcr->default_value |= LPCR_PDEE | LPCR_HDEE | LPCR_EEE | LPCR_DEE |
> +                               LPCR_OEE;
> +        break;
> +    default:
> +        /* P7 and P8 has slightly different PECE bits, mostly because P8 adds
> +         * bit 47 and 48 which are reserved on P7. Here we set them all, which
> +         * will work as expected for both implementations
> +         */
> +        lpcr->default_value |= LPCR_P8_PECE0 | LPCR_P8_PECE1 | LPCR_P8_PECE2 |
> +                               LPCR_P8_PECE3 | LPCR_P8_PECE4;
> +    }
>  
>      /* We should be followed by a CPU reset but update the active value
>       * just in case...

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9

[David Gibson]

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On Mon, Feb 20, 2017 at 06:31:46PM +1100, Balbir Singh wrote:
> On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh wrote:
> > The logical partitioning control register controls a threads operation
> > based on the partition it is currently executing. Add new definitions and
> > update the mask used when writing to the LPCR based on the POWER9 spec.
> > 
> > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> > ---
> >  target/ppc/cpu.h            | 18 ++++++++++++++++++
> >  target/ppc/mmu-hash64.c     |  8 ++++++++
> >  target/ppc/translate_init.c | 24 ++++++++++++++++++------
> >  3 files changed, 44 insertions(+), 6 deletions(-)
> > 
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index bb96dd5..425e79d 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -384,12 +384,19 @@ struct ppc_slb_t {
> >  #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
> >  #define LPCR_VRMASD_SHIFT (63 - 16)
> >  #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
> > +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask */
> > +#define LPCR_PECE_U_SHIFT (63 - 19)
> > +#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
> > +#define LPCR_HVEE         (1ull << (63 - 17)) /* Hypervisor Virt Exit Enable */
> >  #define LPCR_RMLS_SHIFT   (63 - 37)
> >  #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
> >  #define LPCR_ILE          (1ull << (63 - 38))
> >  #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt location */
> >  #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
> > +#define LPCR_UPRT         (1ull << (63 - 41)) /* Use Process Table */
> > +#define LPCR_EVIRT        (1ull << (63 - 42)) /* Enhanced Virtualisation */
> >  #define LPCR_ONL          (1ull << (63 - 45))
> > +#define LPCR_LD           (1ull << (63 - 46)) /* Large Decrementer */
> >  #define LPCR_P7_PECE0     (1ull << (63 - 49))
> >  #define LPCR_P7_PECE1     (1ull << (63 - 50))
> >  #define LPCR_P7_PECE2     (1ull << (63 - 51))
> > @@ -398,11 +405,22 @@ struct ppc_slb_t {
> >  #define LPCR_P8_PECE2     (1ull << (63 - 49))
> >  #define LPCR_P8_PECE3     (1ull << (63 - 50))
> >  #define LPCR_P8_PECE4     (1ull << (63 - 51))
> > +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask */
> > +#define LPCR_PECE_L_SHIFT (63 - 51)
> > +#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
> > +#define LPCR_PDEE         (1ull << (63 - 47)) /* Privileged Doorbell Exit EN */
> > +#define LPCR_HDEE         (1ull << (63 - 48)) /* Hyperv Doorbell Exit Enable */
> > +#define LPCR_EEE          (1ull << (63 - 49)) /* External Exit Enable        */
> > +#define LPCR_DEE          (1ull << (63 - 50)) /* Decrementer Exit Enable     */
> > +#define LPCR_OEE          (1ull << (63 - 51)) /* Other Exit Enable           */
> >  #define LPCR_MER          (1ull << (63 - 52))
> > +#define LPCR_GTSE         (1ull << (63 - 53)) /* Guest Translation Shootdown */
> >  #define LPCR_TC           (1ull << (63 - 54))
> > +#define LPCR_HEIC         (1ull << (63 - 59)) /* HV Extern Interrupt Control */
> >  #define LPCR_LPES0        (1ull << (63 - 60))
> >  #define LPCR_LPES1        (1ull << (63 - 61))
> >  #define LPCR_RMI          (1ull << (63 - 62))
> > +#define LPCR_HVICE        (1ull << (63 - 62)) /* HV Virtualisation Int Enable */
> >  #define LPCR_HDICE        (1ull << (63 - 63))
> 
> This patch is missing
> 
> #define LPCR_HR	(1ull << (63 - 43))	/* HV uses Radix Tree Translation */
> 
> See arch/powerpc/include/asm/reg.h in the Linux kernel. 

Suraj, if you're resending anyway, add this.  It doesn't matter for
non-powernv, of course, but we might as well put the #define in to
document it.

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState

[David Gibson]

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On Mon, Feb 20, 2017 at 03:04:33PM +1100, Suraj Jitindar Singh wrote:
> ISA v3.00 adds the idea of a partition table which is used to store the
> address translation details for all partitions on the system. The partition
> table consists of double word entries indexed by partition id where the second
> double word contains the location of the process table in guest memory. The
> process table is registered by the guest via a h-call.
> 
> We need somewhere to store the address of the process table so we add an entry
> to the sPAPRMachineState struct called patb_entry to represent the second
> doubleword of a single partition table entry corresponding to the current
> guest. We need to store this value so we know if the guest is using radix or
> hash translation and the location of the corresponding process table in guest
> memory. Since we only have a single guest per qemu instance, we only need one
> entry.
> 
> Since the partition table is technically a hypervisor resource we require that
> access to it is abstracted by the virtual hypervisor through the calls
> [set/get]_patbe(). Currently the value of the entry is never set (and thus

You've removed set_patb() as requested, but haven't updated the commit
message here.

> defaults to 0 indicating hash), but it will be required to both implement
> POWER9 kvm support and tcg radix support.
> 
> We also add this field to be migrated as part of the sPAPRMachineState as we
> will need it on the receiving side as the guest will never tell us this
> information again and we need it to perform translation.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>

This looks fine, but will need some reworking to rebase on my
hpt-cleanup patch series.  That might even obsolete the new vhc call.

> 
> ---
> 
> V2->V3:
> - Only add patbe to migration stream if non-zero
> ---
>  hw/ppc/spapr.c         | 29 +++++++++++++++++++++++++++++
>  include/hw/ppc/spapr.h |  1 +
>  target/ppc/cpu.h       |  1 +
>  3 files changed, 31 insertions(+)
> 
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index e465d7a..2fbf193 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -1018,6 +1018,13 @@ static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
>      }
>  }
>  
> +static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
> +{
> +    sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
> +
> +    return spapr->patb_entry;
> +}
> +
>  #define HPTE(_table, _i)   (void *)(((uint64_t *)(_table)) + ((_i) * 2))
>  #define HPTE_VALID(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_VALID)
>  #define HPTE_DIRTY(_hpte)  (tswap64(*((uint64_t *)(_hpte))) & HPTE64_V_HPTE_DIRTY)
> @@ -1141,6 +1148,8 @@ static void ppc_spapr_reset(void)
>      /* Check for unknown sysbus devices */
>      foreach_dynamic_sysbus_device(find_unknown_sysbus_device, NULL);
>  
> +    spapr->patb_entry = 0;
> +
>      /* Allocate and/or reset the hash page table */
>      spapr_reallocate_hpt(spapr,
>                           spapr_hpt_shift_for_ramsize(machine->maxram_size),
> @@ -1327,6 +1336,24 @@ static const VMStateDescription vmstate_spapr_ov5_cas = {
>      },
>  };
>  
> +static bool spapr_patb_entry_needed(void *opaque)
> +{
> +    sPAPRMachineState *spapr = opaque;
> +
> +    return !!spapr->patb_entry;
> +}
> +
> +static const VMStateDescription vmstate_spapr_patb_entry = {
> +    .name = "spapr_patb_entry",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = spapr_patb_entry_needed,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_UINT64(patb_entry, sPAPRMachineState),
> +        VMSTATE_END_OF_LIST()
> +    },
> +};
> +
>  static const VMStateDescription vmstate_spapr = {
>      .name = "spapr",
>      .version_id = 3,
> @@ -1344,6 +1371,7 @@ static const VMStateDescription vmstate_spapr = {
>      },
>      .subsections = (const VMStateDescription*[]) {
>          &vmstate_spapr_ov5_cas,
> +        &vmstate_spapr_patb_entry,
>          NULL
>      }
>  };
> @@ -2733,6 +2761,7 @@ static void spapr_machine_class_init(ObjectClass *oc, void *data)
>      nc->nmi_monitor_handler = spapr_nmi;
>      smc->phb_placement = spapr_phb_placement;
>      vhc->hypercall = emulate_spapr_hypercall;
> +    vhc->get_patbe = spapr_get_patbe;
>  }
>  
>  static const TypeInfo spapr_machine_info = {
> diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> index a2d8964..c6a929a 100644
> --- a/include/hw/ppc/spapr.h
> +++ b/include/hw/ppc/spapr.h
> @@ -63,6 +63,7 @@ struct sPAPRMachineState {
>  
>      void *htab;
>      uint32_t htab_shift;
> +    uint64_t patb_entry; /* Process tbl registed in H_REGISTER_PROCESS_TABLE */
>      hwaddr rma_size;
>      int vrma_adjust;
>      ssize_t rtas_size;
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 425e79d..684d632 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -1218,6 +1218,7 @@ struct PPCVirtualHypervisor {
>  struct PPCVirtualHypervisorClass {
>      InterfaceClass parent;
>      void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu);
> +    uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
>  };
>  
>  #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 06/10] target/ppc: Don't gen an SDR1 on POWER9 and rework register creation

[David Gibson]

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On Mon, Feb 20, 2017 at 03:04:34PM +1100, Suraj Jitindar Singh wrote:
> POWER9 doesn't have a storage description register 1 (SDR1) which is used
> to store the base and size of the hash table. Thus we don't need to
> generate this register on the POWER9 cpu model and thus shouldn't read or
> write to it either. While we're here, init_proc_book3s_64 is a convoluted
> mess which attempts to be a generic function which will then call cpu model
> specific register gen functions, but we're calling it from a cpu model
> specific function (pcc->init_proc) anyway. So instead of going from
> cpu specific function -> generic function -> cpu specific functions, why
> not just call the cpu specific register gen functions directly from the
> cpu specific init_proc() function removing the need for init_proc_book3s_64
> function altogether and hopefully clarifying the cpu model specific
> register generation.
> 
> We rename ppc_hash64_set_sdr1->ppc_hash64_store_hpt to better represent
> that the generic use of the function is to set the htab_[mask/base] and
> sdr1 only if appropriate, and update call sites accordingly.

This should become obsolete once rebased on my hpt-cleanup series -
set_sdr1() shouldn't be called on pseries any more.

> We update ppc_cpu_dump_state so that "info registers" will only display
> the value of sdr1 if the register has been generated.
> 
> Finally, as mentioned above the register generation for the pcc->init_proc
> function for 970, POWER5+, POWER7, POWER8 and POWER9 has been reworked
> for improved clarity. Instead of calling init_proc_book3s_64 which then
> attempts to generate the correct registers through a mess of if
> statements, we remove this function and instead call the appropriate
> register generation functions directly. This follows the register
> generation model followed for earlier cpu models (pre-970) whereby cpu
> specific registers are generated directly in the init_proc function
> and makes it easier to add/remove specific registers for new cpu models.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>

I wholeheartedly endorse the re-organization of the SPR construction.
As noted above it will need a little rework for rebasing, but apart
from that.

Reviewed-by: David Gibson <david@gibson.dropbear.id.au>

> 
> ---
> 
> V2->V3:
> - Add rework of register generation
> ---
>  target/ppc/mmu-hash64.c     |  17 ++-
>  target/ppc/mmu-hash64.h     |   4 +-
>  target/ppc/mmu_helper.c     |   2 +-
>  target/ppc/translate.c      |   7 +-
>  target/ppc/translate_init.c | 316 +++++++++++++++++++++++++++-----------------
>  5 files changed, 218 insertions(+), 128 deletions(-)
> 
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 7c5d589..3e17a9f 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -285,13 +285,12 @@ target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
>  /*
>   * 64-bit hash table MMU handling
>   */
> -void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
> -                         Error **errp)
> +void ppc_hash64_store_hpt(PowerPCCPU *cpu, target_ulong value,
> +                          Error **errp)
>  {
>      CPUPPCState *env = &cpu->env;
>      target_ulong htabsize = value & SDR_64_HTABSIZE;
>  
> -    env->spr[SPR_SDR1] = value;
>      if (htabsize > 28) {
>          error_setg(errp,
>                     "Invalid HTABSIZE 0x" TARGET_FMT_lx" stored in SDR1",
> @@ -300,6 +299,14 @@ void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
>      }
>      env->htab_mask = (1ULL << (htabsize + 18 - 7)) - 1;
>      env->htab_base = value & SDR_64_HTABORG;
> +
> +    switch (env->mmu_model) {
> +    case POWERPC_MMU_3_00:
> +        break; /* Power 9 doesn't have an SDR1 */
> +    default:
> +        env->spr[SPR_SDR1] = value;
> +        break;
> +    }
>  }
>  
>  void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
> @@ -313,8 +320,8 @@ void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
>      } else {
>          env->external_htab = MMU_HASH64_KVM_MANAGED_HPT;
>      }
> -    ppc_hash64_set_sdr1(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
> -                        &local_err);
> +    ppc_hash64_store_hpt(cpu, (target_ulong)(uintptr_t)hpt | (shift - 18),
> +                         &local_err);
>      if (local_err) {
>          error_propagate(errp, local_err);
>          return;
> diff --git a/target/ppc/mmu-hash64.h b/target/ppc/mmu-hash64.h
> index 7a0b7fc..2c00bce 100644
> --- a/target/ppc/mmu-hash64.h
> +++ b/target/ppc/mmu-hash64.h
> @@ -91,8 +91,8 @@ void ppc_hash64_update_rmls(CPUPPCState *env);
>  #define HPTE64_V_1TB_SEG        0x4000000000000000ULL
>  #define HPTE64_V_VRMA_MASK      0x4001ffffff000000ULL
>  
> -void ppc_hash64_set_sdr1(PowerPCCPU *cpu, target_ulong value,
> -                         Error **errp);
> +void ppc_hash64_store_hpt(PowerPCCPU *cpu, target_ulong value,
> +                          Error **errp);
>  void ppc_hash64_set_external_hpt(PowerPCCPU *cpu, void *hpt, int shift,
>                                   Error **errp);
>  
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 172a305..2911266 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -2005,7 +2005,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
>          PowerPCCPU *cpu = ppc_env_get_cpu(env);
>          Error *local_err = NULL;
>  
> -        ppc_hash64_set_sdr1(cpu, value, &local_err);
> +        ppc_hash64_store_hpt(cpu, value, &local_err);
>          if (local_err) {
>              error_report_err(local_err);
>              error_free(local_err);
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index b48abae..473a40a 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -6850,9 +6850,12 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
>      case POWERPC_MMU_2_06a:
>      case POWERPC_MMU_2_07:
>      case POWERPC_MMU_2_07a:
> +    case POWERPC_MMU_3_00:
>  #endif
> -        cpu_fprintf(f, " SDR1 " TARGET_FMT_lx "   DAR " TARGET_FMT_lx
> -                       "  DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
> +        if (env->spr_cb[SPR_SDR1].name) {
> +            cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " ", env->spr[SPR_SDR1]);
> +        }
> +        cpu_fprintf(f, "  DAR " TARGET_FMT_lx "  DSISR " TARGET_FMT_lx "\n",
>                      env->spr[SPR_DAR], env->spr[SPR_DSISR]);
>          break;
>      case POWERPC_MMU_BOOKE206:
> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index be35cbd..32c1619 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -723,7 +723,7 @@ static void gen_spr_generic (CPUPPCState *env)
>  }
>  
>  /* SPR common to all non-embedded PowerPC, including 601 */
> -static void gen_spr_ne_601 (CPUPPCState *env)
> +static void gen_spr_ne_601(CPUPPCState *env)
>  {
>      /* Exception processing */
>      spr_register_kvm(env, SPR_DSISR, "DSISR",
> @@ -739,7 +739,11 @@ static void gen_spr_ne_601 (CPUPPCState *env)
>                   SPR_NOACCESS, SPR_NOACCESS,
>                   &spr_read_decr, &spr_write_decr,
>                   0x00000000);
> -    /* Memory management */
> +}
> +
> +/* Storage Description Register 1 */
> +static void gen_spr_sdr1(CPUPPCState *env)
> +{
>      spr_register(env, SPR_SDR1, "SDR1",
>                   SPR_NOACCESS, SPR_NOACCESS,
>                   &spr_read_generic, &spr_write_sdr1,
> @@ -1168,7 +1172,7 @@ static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
>  }
>  #endif /* CONFIG_USER_ONLY */
>  
> -static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
> +static void gen_spr_amr(CPUPPCState *env)
>  {
>  #ifndef CONFIG_USER_ONLY
>      /* Virtual Page Class Key protection */
> @@ -1194,13 +1198,17 @@ static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
>                      SPR_NOACCESS, SPR_NOACCESS,
>                      &spr_read_generic, &spr_write_generic,
>                      0);
> -    if (has_iamr) {
> -        spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
> -                            SPR_NOACCESS, SPR_NOACCESS,
> -                            &spr_read_generic, &spr_write_iamr,
> -                            &spr_read_generic, &spr_write_generic,
> -                            KVM_REG_PPC_IAMR, 0);
> -    }
> +#endif /* !CONFIG_USER_ONLY */
> +}
> +
> +static void gen_spr_iamr(CPUPPCState *env)
> +{
> +#ifndef CONFIG_USER_ONLY
> +    spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
> +                        SPR_NOACCESS, SPR_NOACCESS,
> +                        &spr_read_generic, &spr_write_iamr,
> +                        &spr_read_generic, &spr_write_generic,
> +                        KVM_REG_PPC_IAMR, 0);
>  #endif /* !CONFIG_USER_ONLY */
>  }
>  #endif /* TARGET_PPC64 */
> @@ -4410,6 +4418,7 @@ POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
>  static void init_proc_G2 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_G2_755(env);
>      gen_spr_G2(env);
>      /* Time base */
> @@ -4488,6 +4497,7 @@ POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
>  static void init_proc_G2LE (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_G2_755(env);
>      gen_spr_G2(env);
>      /* Time base */
> @@ -4723,6 +4733,7 @@ POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
>  static void init_proc_e300 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_603(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -5222,6 +5233,7 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
>  static void init_proc_601 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_601(env);
>      /* Hardware implementation registers */
>      /* XXX : not implemented */
> @@ -5336,6 +5348,7 @@ POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
>  static void init_proc_602 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_602(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -5405,6 +5418,7 @@ POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
>  static void init_proc_603 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_603(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -5471,6 +5485,7 @@ POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
>  static void init_proc_603E (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_603(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -5537,6 +5552,7 @@ POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
>  static void init_proc_604 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_604(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -5600,6 +5616,7 @@ POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
>  static void init_proc_604E (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_604(env);
>      /* XXX : not implemented */
>      spr_register(env, SPR_7XX_MMCR1, "MMCR1",
> @@ -5683,6 +5700,7 @@ POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
>  static void init_proc_740 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -5753,6 +5771,7 @@ POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
>  static void init_proc_750 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* XXX : not implemented */
>      spr_register(env, SPR_L2CR, "L2CR",
> @@ -5831,6 +5850,7 @@ POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
>  static void init_proc_750cl (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* XXX : not implemented */
>      spr_register(env, SPR_L2CR, "L2CR",
> @@ -6032,6 +6052,7 @@ POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
>  static void init_proc_750cx (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* XXX : not implemented */
>      spr_register(env, SPR_L2CR, "L2CR",
> @@ -6114,6 +6135,7 @@ POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
>  static void init_proc_750fx (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* XXX : not implemented */
>      spr_register(env, SPR_L2CR, "L2CR",
> @@ -6201,6 +6223,7 @@ POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
>  static void init_proc_750gx (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* XXX : not implemented (XXX: different from 750fx) */
>      spr_register(env, SPR_L2CR, "L2CR",
> @@ -6288,6 +6311,7 @@ POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
>  static void init_proc_745 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      gen_spr_G2_755(env);
>      /* Time base */
> @@ -6363,6 +6387,7 @@ POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
>  static void init_proc_755 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      gen_spr_G2_755(env);
>      /* Time base */
> @@ -6449,6 +6474,7 @@ POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
>  static void init_proc_7400 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -6527,6 +6553,7 @@ POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
>  static void init_proc_7410 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -6611,6 +6638,7 @@ POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
>  static void init_proc_7440 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -6718,6 +6746,7 @@ POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
>  static void init_proc_7450 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -6851,6 +6880,7 @@ POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
>  static void init_proc_7445 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -6987,6 +7017,7 @@ POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
>  static void init_proc_7455 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -7125,6 +7156,7 @@ POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
>  static void init_proc_7457 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -7287,6 +7319,7 @@ POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
>  static void init_proc_e600 (CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
> +    gen_spr_sdr1(env);
>      gen_spr_7xx(env);
>      /* Time base */
>      gen_tbl(env);
> @@ -7432,15 +7465,6 @@ POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
>  #define POWERPC970_HID5_INIT 0x00000000
>  #endif
>  
> -enum BOOK3S_CPU_TYPE {
> -    BOOK3S_CPU_970,
> -    BOOK3S_CPU_POWER5PLUS,
> -    BOOK3S_CPU_POWER6,
> -    BOOK3S_CPU_POWER7,
> -    BOOK3S_CPU_POWER8,
> -    BOOK3S_CPU_POWER9
> -};
> -
>  static void gen_fscr_facility_check(DisasContext *ctx, int facility_sprn,
>                                      int bit, int sprn, int cause)
>  {
> @@ -7528,7 +7552,7 @@ static void gen_spr_970_hior(CPUPPCState *env)
>                   0x00000000);
>  }
>  
> -static void gen_spr_book3s_common(CPUPPCState *env)
> +static void gen_spr_book3s_ctrl(CPUPPCState *env)
>  {
>      spr_register(env, SPR_CTRL, "SPR_CTRL",
>                   SPR_NOACCESS, SPR_NOACCESS,
> @@ -8198,112 +8222,42 @@ static void gen_spr_power8_rpr(CPUPPCState *env)
>  #endif
>  }
>  
> -static void init_proc_book3s_64(CPUPPCState *env, int version)
> +static void init_proc_book3s_common(CPUPPCState *env)
>  {
>      gen_spr_ne_601(env);
>      gen_tbl(env);
>      gen_spr_book3s_altivec(env);
>      gen_spr_book3s_pmu_sup(env);
>      gen_spr_book3s_pmu_user(env);
> -    gen_spr_book3s_common(env);
> +    gen_spr_book3s_ctrl(env);
> +}
>  
> -    switch (version) {
> -    case BOOK3S_CPU_970:
> -    case BOOK3S_CPU_POWER5PLUS:
> -        gen_spr_970_hid(env);
> -        gen_spr_970_hior(env);
> -        gen_low_BATs(env);
> -        gen_spr_970_pmu_sup(env);
> -        gen_spr_970_pmu_user(env);
> -        break;
> -    case BOOK3S_CPU_POWER7:
> -    case BOOK3S_CPU_POWER8:
> -    case BOOK3S_CPU_POWER9:
> -        gen_spr_book3s_ids(env);
> -        gen_spr_amr(env, version >= BOOK3S_CPU_POWER8);
> -        gen_spr_book3s_purr(env);
> -        env->ci_large_pages = true;
> -        break;
> -    default:
> -        g_assert_not_reached();
> -    }
> -    if (version >= BOOK3S_CPU_POWER5PLUS) {
> -        gen_spr_power5p_common(env);
> -        gen_spr_power5p_lpar(env);
> -        gen_spr_power5p_ear(env);
> -    } else {
> -        gen_spr_970_lpar(env);
> -    }
> -    if (version == BOOK3S_CPU_970) {
> -        gen_spr_970_dbg(env);
> -    }
> -    if (version >= BOOK3S_CPU_POWER6) {
> -        gen_spr_power6_common(env);
> -        gen_spr_power6_dbg(env);
> -    }
> -    if (version == BOOK3S_CPU_POWER7) {
> -        gen_spr_power7_book4(env);
> -    }
> -    if (version >= BOOK3S_CPU_POWER8) {
> -        gen_spr_power8_tce_address_control(env);
> -        gen_spr_power8_ids(env);
> -        gen_spr_power8_ebb(env);
> -        gen_spr_power8_fscr(env);
> -        gen_spr_power8_pmu_sup(env);
> -        gen_spr_power8_pmu_user(env);
> -        gen_spr_power8_tm(env);
> -        gen_spr_power8_pspb(env);
> -        gen_spr_vtb(env);
> -        gen_spr_power8_ic(env);
> -        gen_spr_power8_book4(env);
> -        gen_spr_power8_rpr(env);
> -    }
> -    if (version < BOOK3S_CPU_POWER8) {
> -        gen_spr_book3s_dbg(env);
> -    } else {
> -        gen_spr_book3s_207_dbg(env);
> -    }
> +static void init_proc_970(CPUPPCState *env)
> +{
> +    /* Common Registers */
> +    init_proc_book3s_common(env);
> +    gen_spr_sdr1(env);
> +    gen_spr_book3s_dbg(env);
> +
> +    /* 970 Specific Registers */
> +    gen_spr_970_hid(env);
> +    gen_spr_970_hior(env);
> +    gen_low_BATs(env);
> +    gen_spr_970_pmu_sup(env);
> +    gen_spr_970_pmu_user(env);
> +    gen_spr_970_lpar(env);
> +    gen_spr_970_dbg(env);
> +
> +    /* env variables */
>  #if !defined(CONFIG_USER_ONLY)
> -    switch (version) {
> -    case BOOK3S_CPU_970:
> -    case BOOK3S_CPU_POWER5PLUS:
> -        env->slb_nr = 64;
> -        break;
> -    case BOOK3S_CPU_POWER7:
> -    case BOOK3S_CPU_POWER8:
> -    case BOOK3S_CPU_POWER9:
> -    default:
> -        env->slb_nr = 32;
> -        break;
> -    }
> +    env->slb_nr = 64;
>  #endif
> -    /* Allocate hardware IRQ controller */
> -    switch (version) {
> -    case BOOK3S_CPU_970:
> -    case BOOK3S_CPU_POWER5PLUS:
> -        init_excp_970(env);
> -        ppc970_irq_init(ppc_env_get_cpu(env));
> -        break;
> -    case BOOK3S_CPU_POWER7:
> -        init_excp_POWER7(env);
> -        ppcPOWER7_irq_init(ppc_env_get_cpu(env));
> -        break;
> -    case BOOK3S_CPU_POWER8:
> -    case BOOK3S_CPU_POWER9:
> -        init_excp_POWER8(env);
> -        ppcPOWER7_irq_init(ppc_env_get_cpu(env));
> -        break;
> -    default:
> -        g_assert_not_reached();
> -    }
> -
>      env->dcache_line_size = 128;
>      env->icache_line_size = 128;
> -}
>  
> -static void init_proc_970(CPUPPCState *env)
> -{
> -    init_proc_book3s_64(env, BOOK3S_CPU_970);
> +    /* Allocate hardware IRQ controller */
> +    init_excp_970(env);
> +    ppc970_irq_init(ppc_env_get_cpu(env));
>  }
>  
>  POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
> @@ -8355,7 +8309,31 @@ POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
>  
>  static void init_proc_power5plus(CPUPPCState *env)
>  {
> -    init_proc_book3s_64(env, BOOK3S_CPU_POWER5PLUS);
> +    /* Common Registers */
> +    init_proc_book3s_common(env);
> +    gen_spr_sdr1(env);
> +    gen_spr_book3s_dbg(env);
> +
> +    /* POWER5+ Specific Registers */
> +    gen_spr_970_hid(env);
> +    gen_spr_970_hior(env);
> +    gen_low_BATs(env);
> +    gen_spr_970_pmu_sup(env);
> +    gen_spr_970_pmu_user(env);
> +    gen_spr_power5p_common(env);
> +    gen_spr_power5p_lpar(env);
> +    gen_spr_power5p_ear(env);
> +
> +    /* env variables */
> +#if !defined(CONFIG_USER_ONLY)
> +    env->slb_nr = 64;
> +#endif
> +    env->dcache_line_size = 128;
> +    env->icache_line_size = 128;
> +
> +    /* Allocate hardware IRQ controller */
> +    init_excp_970(env);
> +    ppc970_irq_init(ppc_env_get_cpu(env));
>  }
>  
>  POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
> @@ -8508,7 +8486,33 @@ static const struct ppc_segment_page_sizes POWER7_POWER8_sps = {
>  
>  static void init_proc_POWER7 (CPUPPCState *env)
>  {
> -    init_proc_book3s_64(env, BOOK3S_CPU_POWER7);
> +    /* Common Registers */
> +    init_proc_book3s_common(env);
> +    gen_spr_sdr1(env);
> +    gen_spr_book3s_dbg(env);
> +
> +    /* POWER7 Specific Registers */
> +    gen_spr_book3s_ids(env);
> +    gen_spr_amr(env);
> +    gen_spr_book3s_purr(env);
> +    gen_spr_power5p_common(env);
> +    gen_spr_power5p_lpar(env);
> +    gen_spr_power5p_ear(env);
> +    gen_spr_power6_common(env);
> +    gen_spr_power6_dbg(env);
> +    gen_spr_power7_book4(env);
> +
> +    /* env variables */
> +#if !defined(CONFIG_USER_ONLY)
> +    env->slb_nr = 32;
> +#endif
> +    env->ci_large_pages = true;
> +    env->dcache_line_size = 128;
> +    env->icache_line_size = 128;
> +
> +    /* Allocate hardware IRQ controller */
> +    init_excp_POWER7(env);
> +    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
>  }
>  
>  static bool ppc_pvr_match_power7(PowerPCCPUClass *pcc, uint32_t pvr)
> @@ -8624,7 +8628,45 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
>  
>  static void init_proc_POWER8(CPUPPCState *env)
>  {
> -    init_proc_book3s_64(env, BOOK3S_CPU_POWER8);
> +    /* Common Registers */
> +    init_proc_book3s_common(env);
> +    gen_spr_sdr1(env);
> +    gen_spr_book3s_207_dbg(env);
> +
> +    /* POWER8 Specific Registers */
> +    gen_spr_book3s_ids(env);
> +    gen_spr_amr(env);
> +    gen_spr_iamr(env);
> +    gen_spr_book3s_purr(env);
> +    gen_spr_power5p_common(env);
> +    gen_spr_power5p_lpar(env);
> +    gen_spr_power5p_ear(env);
> +    gen_spr_power6_common(env);
> +    gen_spr_power6_dbg(env);
> +    gen_spr_power8_tce_address_control(env);
> +    gen_spr_power8_ids(env);
> +    gen_spr_power8_ebb(env);
> +    gen_spr_power8_fscr(env);
> +    gen_spr_power8_pmu_sup(env);
> +    gen_spr_power8_pmu_user(env);
> +    gen_spr_power8_tm(env);
> +    gen_spr_power8_pspb(env);
> +    gen_spr_vtb(env);
> +    gen_spr_power8_ic(env);
> +    gen_spr_power8_book4(env);
> +    gen_spr_power8_rpr(env);
> +
> +    /* env variables */
> +#if !defined(CONFIG_USER_ONLY)
> +    env->slb_nr = 32;
> +#endif
> +    env->ci_large_pages = true;
> +    env->dcache_line_size = 128;
> +    env->icache_line_size = 128;
> +
> +    /* Allocate hardware IRQ controller */
> +    init_excp_POWER8(env);
> +    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
>  }
>  
>  static bool ppc_pvr_match_power8(PowerPCCPUClass *pcc, uint32_t pvr)
> @@ -8752,9 +8794,47 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
>      pcc->l1_icache_size = 0x8000;
>      pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
>  }
> +
>  static void init_proc_POWER9(CPUPPCState *env)
>  {
> -    init_proc_book3s_64(env, BOOK3S_CPU_POWER9);
> +    /* Common Registers */
> +    init_proc_book3s_common(env);
> +    gen_spr_book3s_207_dbg(env);
> +
> +    /* POWER8 Specific Registers */
> +    gen_spr_book3s_ids(env);
> +    gen_spr_amr(env);
> +    gen_spr_iamr(env);
> +    gen_spr_book3s_purr(env);
> +    gen_spr_power5p_common(env);
> +    gen_spr_power5p_lpar(env);
> +    gen_spr_power5p_ear(env);
> +    gen_spr_power6_common(env);
> +    gen_spr_power6_dbg(env);
> +    gen_spr_power8_tce_address_control(env);
> +    gen_spr_power8_ids(env);
> +    gen_spr_power8_ebb(env);
> +    gen_spr_power8_fscr(env);
> +    gen_spr_power8_pmu_sup(env);
> +    gen_spr_power8_pmu_user(env);
> +    gen_spr_power8_tm(env);
> +    gen_spr_power8_pspb(env);
> +    gen_spr_vtb(env);
> +    gen_spr_power8_ic(env);
> +    gen_spr_power8_book4(env);
> +    gen_spr_power8_rpr(env);
> +
> +    /* env variables */
> +#if !defined(CONFIG_USER_ONLY)
> +    env->slb_nr = 32;
> +#endif
> +    env->ci_large_pages = true;
> +    env->dcache_line_size = 128;
> +    env->icache_line_size = 128;
> +
> +    /* Allocate hardware IRQ controller */
> +    init_excp_POWER8(env);
> +    ppcPOWER7_irq_init(ppc_env_get_cpu(env));
>  }
>  
>  static bool ppc_pvr_match_power9(PowerPCCPUClass *pcc, uint32_t pvr)

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler

[David Gibson]

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On Mon, Feb 20, 2017 at 03:04:35PM +1100, Suraj Jitindar Singh wrote:
> Add a new mmu fault handler for the POWER9 cpu and add it as the handler
> for the POWER9 cpu definition.
> 
> This handler checks if the guest is radix or hash based on the value in the
> partition table entry and calls the correct fault handler accordingly.
> 
> The hash fault handling code has also been updated to check if the
> partition is using segment tables.
> 
> Currently only legacy hash (no segment tables) is supported.
> 
> Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> 
> ---
> 
> V2->V3:
> - error_report on attempt to use segment tables instead of just LOG()
> - Rename mmu.h -> mmu-book3s-v3.h
> ---
>  target/ppc/mmu-book3s-v3.h  | 50 +++++++++++++++++++++++++++++++++++++++++++++
>  target/ppc/mmu-hash64.c     |  8 ++++++++
>  target/ppc/mmu_helper.c     | 40 ++++++++++++++++++++++++++++++++++++
>  target/ppc/translate_init.c |  3 ++-
>  4 files changed, 100 insertions(+), 1 deletion(-)
>  create mode 100644 target/ppc/mmu-book3s-v3.h
> 
> diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-v3.h
> new file mode 100644
> index 0000000..9375921
> --- /dev/null
> +++ b/target/ppc/mmu-book3s-v3.h
> @@ -0,0 +1,50 @@
> +/*
> + *  PowerPC emulation generic mmu definitions for qemu.
> + *
> + *  Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License as published by the Free Software Foundation; either
> + * version 2 of the License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, see <http://www.gnu.org/licenses/>.
> + */
> +
> +#ifndef MMU_H
> +#define MMU_H
> +
> +#ifndef CONFIG_USER_ONLY
> +
> +/* Partition Table Entry Fields */
> +#define PATBE1_GR 0x8000000000000000
> +
> +#ifdef TARGET_PPC64
> +
> +static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
> +{
> +    return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
> +}
> +
> +static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
> +{
> +    PPCVirtualHypervisorClass *vhc =
> +        PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> +
> +    return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> +}
> +
> +int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
> +                              int mmu_idx);
> +
> +#endif /* TARGET_PPC64 */
> +
> +#endif /* CONFIG_USER_ONLY */
> +
> +#endif /* MMU_H */
> diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> index 3e17a9f..a581b50 100644
> --- a/target/ppc/mmu-hash64.c
> +++ b/target/ppc/mmu-hash64.c
> @@ -27,6 +27,7 @@
>  #include "kvm_ppc.h"
>  #include "mmu-hash64.h"
>  #include "exec/log.h"
> +#include "mmu-book3s-v3.h"
>  
>  //#define DEBUG_SLB
>  
> @@ -767,6 +768,13 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr,
>      /* 2. Translation is on, so look up the SLB */
>      slb = slb_lookup(cpu, eaddr);
>      if (!slb) {
> +        /* No entry found, check if in-memory segment tables are in use */
> +        if (ppc64_use_proc_tbl(cpu)) {
> +            /* TODO - Unsupported */
> +            error_report("Segment Table Support Unimplemented");
> +            abort();
> +        }
> +        /* Segment still not found, generate the appropriate interrupt */
>          if (rwx == 2) {
>              cs->exception_index = POWERPC_EXCP_ISEG;
>              env->error_code = 0;
> diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> index 2911266..527123c 100644
> --- a/target/ppc/mmu_helper.c
> +++ b/target/ppc/mmu_helper.c
> @@ -28,6 +28,8 @@
>  #include "exec/cpu_ldst.h"
>  #include "exec/log.h"
>  #include "helper_regs.h"
> +#include "qemu/error-report.h"
> +#include "mmu-book3s-v3.h"
>  
>  //#define DEBUG_MMU
>  //#define DEBUG_BATS
> @@ -1280,6 +1282,17 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
>      case POWERPC_MMU_2_07a:
>          dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
>          break;
> +    case POWERPC_MMU_3_00:
> +        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> +            /* TODO - Unsupported */
> +        } else {
> +            if (ppc64_use_proc_tbl(ppc_env_get_cpu(env))) {
> +                /* TODO - Unsupported */
> +            } else {
> +                dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> +                break;
> +            }
> +        }
>  #endif
>      default:
>          qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__);
> @@ -1421,6 +1434,17 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
>      case POWERPC_MMU_2_07:
>      case POWERPC_MMU_2_07a:
>          return ppc_hash64_get_phys_page_debug(cpu, addr);
> +    case POWERPC_MMU_3_00:
> +        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> +            /* TODO - Unsupported */
> +        } else {
> +            if (ppc64_use_proc_tbl(ppc_env_get_cpu(env))) {
> +                /* TODO - Unsupported */
> +            } else {
> +                return ppc_hash64_get_phys_page_debug(cpu, addr);
> +            }

I don't think you need the inner if in this case -
ppc_hash64_get_phys_page_debug() will be basically right for both
cases, except it will (eventually) need an internal check to consult
segment tables if they're there.

One interesting wrinkle here is that this debug path is exactly a case
where it could be useful to consult the segment tables if the OS
provides them, even if the actual hardware MMU doesn't use them.

> +        }
> +        break;
>  #endif
>  
>      case POWERPC_MMU_32B:
> @@ -2907,3 +2931,19 @@ void tlb_fill(CPUState *cs, target_ulong addr, MMUAccessType access_type,
>                                 retaddr);
>      }
>  }
> +
> +/******************************************************************************/
> +
> +/* ISA v3.00 (POWER9) Generic MMU Helpers */
> +
> +int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx,
> +                              int mmu_idx)
> +{
> +    if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
> +        /* TODO - Unsupported */
> +        error_report("Guest Radix Support Unimplemented");
> +        abort();
> +    } else { /* Guest uses hash */
> +        return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx, mmu_idx);
> +    }
> +}

This can go into a new mmu-books-v3.c, small for now, but it can take
the radix stuff as well once it gets implemented.

> diff --git a/target/ppc/translate_init.c b/target/ppc/translate_init.c
> index 32c1619..7661c21 100644
> --- a/target/ppc/translate_init.c
> +++ b/target/ppc/translate_init.c
> @@ -32,6 +32,7 @@
>  #include "qapi/visitor.h"
>  #include "hw/qdev-properties.h"
>  #include "hw/ppc/ppc.h"
> +#include "mmu-book3s-v3.h"
>  
>  //#define PPC_DUMP_CPU
>  //#define PPC_DEBUG_SPR
> @@ -8898,7 +8899,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
>                      (1ull << MSR_LE);
>      pcc->mmu_model = POWERPC_MMU_3_00;
>  #if defined(CONFIG_SOFTMMU)
> -    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> +    pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
>      /* segment page size remain the same */
>      pcc->sps = &POWER7_POWER8_sps;
>  #endif

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 00/10] target/ppc: Implement POWER9 pseries tcg legacy support

[David Gibson]

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On Mon, Feb 20, 2017 at 03:04:28PM +1100, Suraj Jitindar Singh wrote:
> This is V3 of the patch series to implement tcg emulation support for a
> POWER9 cpu model for the pseries machine type running a legacy kernel.
> That is a kernel which doesn't use the new radix mmu mode or the new hash
> mmu mode with segment tables.
> 
> To use a POWER9 cpu provide the command line option "-cpu POWER9".
> 
> This series attempts to avoid precluding KVM-HV support for the POWER9
> cpu model but doesn't attempt to support KVM-PR or the powernv machine
> for the POWER9 cpu model as these aren't currently supported or
> implemented and further code changes will be required in the event these
> are implemented.
> 
> This series is used as a base to implement radix support.

This is looking pretty good.  Main thing is it will need some rework
to rebase on my HPT cleanup as discussed.  I've made a few other
comments, but they're all small things.
> 
> The changes from V2 are as follows:
> 
>  - Only migrate the partition table entry on non-zero value
>  - Change how register generation works to simplify adding/removing
>    registers
>  - Rename mmu.h -> mmu-book3s-v3.h
>  - Error report and abort on attempt to use segment tables
> 
> Suraj Jitindar Singh (10):
>   target/ppc/POWER9: Add ISAv3.00 MMU definition
>   target/ppc: Fix LPCR DPFD mask define
>   target/ppc/POWER9: Adapt LPCR handling for POWER9
>   target/ppc/POWER9: Direct all instr and data storage interrupts to the
>     hypv
>   target/ppc: Add patb_entry to sPAPRMachineState
>   target/ppc: Don't gen an SDR1 on POWER9 and rework register creation
>   target/ppc/POWER9: Add POWER9 mmu fault handler
>   target/ppc/POWER9: Add POWER9 pa-features definition
>   target/ppc/POWER9: Add cpu_has_work function for POWER9
>   hw/ppc/spapr: Add POWER9 to pseries cpu models
> 
>  hw/ppc/spapr.c              |  47 ++++++
>  hw/ppc/spapr_cpu_core.c     |   3 +
>  include/hw/ppc/spapr.h      |   1 +
>  target/ppc/cpu-qom.h        |   5 +-
>  target/ppc/cpu.h            |  21 ++-
>  target/ppc/mmu-book3s-v3.h  |  50 ++++++
>  target/ppc/mmu-hash64.c     |  53 +++++-
>  target/ppc/mmu-hash64.h     |   4 +-
>  target/ppc/mmu_helper.c     |  44 ++++-
>  target/ppc/translate.c      |   7 +-
>  target/ppc/translate_init.c | 391 ++++++++++++++++++++++++++++++--------------
>  11 files changed, 485 insertions(+), 141 deletions(-)
>  create mode 100644 target/ppc/mmu-book3s-v3.h
> 

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 01/10] target/ppc/POWER9: Add ISAv3.00 MMU definition

[Suraj Jitindar Singh]

On Thu, 2017-02-23 at 14:43 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 04:16:26PM +1100, Balbir Singh wrote:
> > 
> > On Mon, Feb 20, 2017 at 03:04:29PM +1100, Suraj Jitindar Singh
> > wrote:
> > > 
> > > POWER9 processors implement the mmu as defined in version 3.00 of
> > > the ISA.
> > > 
> > > Add a definition for this mmu model and set the POWER9 cpu model
> > > to use
> > > this mmu model.
> > > 
> > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> > > ---
> > >  target/ppc/cpu-qom.h        | 5 ++++-
> > >  target/ppc/mmu_helper.c     | 2 ++
> > >  target/ppc/translate_init.c | 3 +--
> > >  3 files changed, 7 insertions(+), 3 deletions(-)
> > > 
> > > diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h
> > > index b7977ba..4e3132b 100644
> > > --- a/target/ppc/cpu-qom.h
> > > +++ b/target/ppc/cpu-qom.h
> > > @@ -86,10 +86,13 @@ enum powerpc_mmu_t {
> > >      POWERPC_MMU_2_07       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > >                               | POWERPC_MMU_64K
> > >                               | POWERPC_MMU_AMR | 0x00000004,
> > > -    /* FIXME Add POWERPC_MMU_3_OO defines */
> > >      /* Architecture 2.07 "degraded" (no 1T
> > > segments)           */
> > >      POWERPC_MMU_2_07a      = POWERPC_MMU_64 | POWERPC_MMU_AMR
> > >                               | 0x00000004,
> > > +    /* Architecture 3.00
> > > variant                               */
> > > +    POWERPC_MMU_3_00       = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
> > > +                             | POWERPC_MMU_64K
> > > +                             | POWERPC_MMU_AMR | 0x00000005,
> > I wonder if we need a POWERPC_MMU_RADIX that we can then attach
> > with future versions
> That's probably a good idea.
> 

As discussed on IRC, will add an mmu feature flag POWERPC_MMU_V3

Re: [Qemu-devel] [Qemu-ppc] [QEMU-PPC] [PATCH V3 03/10] target/ppc/POWER9: Adapt LPCR handling for POWER9

[Suraj Jitindar Singh]

On Thu, 2017-02-23 at 14:47 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 06:31:46PM +1100, Balbir Singh wrote:
> > 
> > On Mon, Feb 20, 2017 at 03:04:31PM +1100, Suraj Jitindar Singh
> > wrote:
> > > 
> > > The logical partitioning control register controls a threads
> > > operation
> > > based on the partition it is currently executing. Add new
> > > definitions and
> > > update the mask used when writing to the LPCR based on the POWER9
> > > spec.
> > > 
> > > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> > > ---
> > >  target/ppc/cpu.h            | 18 ++++++++++++++++++
> > >  target/ppc/mmu-hash64.c     |  8 ++++++++
> > >  target/ppc/translate_init.c | 24 ++++++++++++++++++------
> > >  3 files changed, 44 insertions(+), 6 deletions(-)
> > > 
> > > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > > index bb96dd5..425e79d 100644
> > > --- a/target/ppc/cpu.h
> > > +++ b/target/ppc/cpu.h
> > > @@ -384,12 +384,19 @@ struct ppc_slb_t {
> > >  #define LPCR_DPFD         (0x7ull << LPCR_DPFD_SHIFT)
> > >  #define LPCR_VRMASD_SHIFT (63 - 16)
> > >  #define LPCR_VRMASD       (0x1full << LPCR_VRMASD_SHIFT)
> > > +/* P9: Power-saving mode Exit Cause Enable (Upper Section) Mask
> > > */
> > > +#define LPCR_PECE_U_SHIFT (63 - 19)
> > > +#define LPCR_PECE_U_MASK  (0x7ull << LPCR_PECE_U_SHIFT)
> > > +#define LPCR_HVEE         (1ull << (63 - 17)) /* Hypervisor Virt
> > > Exit Enable */
> > >  #define LPCR_RMLS_SHIFT   (63 - 37)
> > >  #define LPCR_RMLS         (0xfull << LPCR_RMLS_SHIFT)
> > >  #define LPCR_ILE          (1ull << (63 - 38))
> > >  #define LPCR_AIL_SHIFT    (63 - 40)      /* Alternate interrupt
> > > location */
> > >  #define LPCR_AIL          (3ull << LPCR_AIL_SHIFT)
> > > +#define LPCR_UPRT         (1ull << (63 - 41)) /* Use Process
> > > Table */
> > > +#define LPCR_EVIRT        (1ull << (63 - 42)) /* Enhanced
> > > Virtualisation */
> > >  #define LPCR_ONL          (1ull << (63 - 45))
> > > +#define LPCR_LD           (1ull << (63 - 46)) /* Large
> > > Decrementer */
> > >  #define LPCR_P7_PECE0     (1ull << (63 - 49))
> > >  #define LPCR_P7_PECE1     (1ull << (63 - 50))
> > >  #define LPCR_P7_PECE2     (1ull << (63 - 51))
> > > @@ -398,11 +405,22 @@ struct ppc_slb_t {
> > >  #define LPCR_P8_PECE2     (1ull << (63 - 49))
> > >  #define LPCR_P8_PECE3     (1ull << (63 - 50))
> > >  #define LPCR_P8_PECE4     (1ull << (63 - 51))
> > > +/* P9: Power-saving mode Exit Cause Enable (Lower Section) Mask
> > > */
> > > +#define LPCR_PECE_L_SHIFT (63 - 51)
> > > +#define LPCR_PECE_L_MASK  (0x1full << LPCR_PECE_L_SHIFT)
> > > +#define LPCR_PDEE         (1ull << (63 - 47)) /* Privileged
> > > Doorbell Exit EN */
> > > +#define LPCR_HDEE         (1ull << (63 - 48)) /* Hyperv Doorbell
> > > Exit Enable */
> > > +#define LPCR_EEE          (1ull << (63 - 49)) /* External Exit
> > > Enable        */
> > > +#define LPCR_DEE          (1ull << (63 - 50)) /* Decrementer
> > > Exit Enable     */
> > > +#define LPCR_OEE          (1ull << (63 - 51)) /* Other Exit
> > > Enable           */
> > >  #define LPCR_MER          (1ull << (63 - 52))
> > > +#define LPCR_GTSE         (1ull << (63 - 53)) /* Guest
> > > Translation Shootdown */
> > >  #define LPCR_TC           (1ull << (63 - 54))
> > > +#define LPCR_HEIC         (1ull << (63 - 59)) /* HV Extern
> > > Interrupt Control */
> > >  #define LPCR_LPES0        (1ull << (63 - 60))
> > >  #define LPCR_LPES1        (1ull << (63 - 61))
> > >  #define LPCR_RMI          (1ull << (63 - 62))
> > > +#define LPCR_HVICE        (1ull << (63 - 62)) /* HV
> > > Virtualisation Int Enable */
> > >  #define LPCR_HDICE        (1ull << (63 - 63))
> > This patch is missing
> > 
> > #define LPCR_HR	(1ull << (63 - 43))	/* HV uses Radix
> > Tree Translation */
> > 
> > See arch/powerpc/include/asm/reg.h in the Linux kernel. 
> Suraj, if you're resending anyway, add this.  It doesn't matter for
> non-powernv, of course, but we might as well put the #define in to
> document it.
> 

Yeah adding a define can't hurt

Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 05/10] target/ppc: Add patb_entry to sPAPRMachineState

[Suraj Jitindar Singh]

On Thu, 2017-02-23 at 14:50 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 03:04:33PM +1100, Suraj Jitindar Singh wrote:
> > 
> > ISA v3.00 adds the idea of a partition table which is used to store
> > the
> > address translation details for all partitions on the system. The
> > partition
> > table consists of double word entries indexed by partition id where
> > the second
> > double word contains the location of the process table in guest
> > memory. The
> > process table is registered by the guest via a h-call.
> > 
> > We need somewhere to store the address of the process table so we
> > add an entry
> > to the sPAPRMachineState struct called patb_entry to represent the
> > second
> > doubleword of a single partition table entry corresponding to the
> > current
> > guest. We need to store this value so we know if the guest is using
> > radix or
> > hash translation and the location of the corresponding process
> > table in guest
> > memory. Since we only have a single guest per qemu instance, we
> > only need one
> > entry.
> > 
> > Since the partition table is technically a hypervisor resource we
> > require that
> > access to it is abstracted by the virtual hypervisor through the
> > calls
> > [set/get]_patbe(). Currently the value of the entry is never set
> > (and thus
> You've removed set_patb() as requested, but haven't updated the
> commit
> message here.

Wooops... :)
> 
> > 
> > defaults to 0 indicating hash), but it will be required to both
> > implement
> > POWER9 kvm support and tcg radix support.
> > 
> > We also add this field to be migrated as part of the
> > sPAPRMachineState as we
> > will need it on the receiving side as the guest will never tell us
> > this
> > information again and we need it to perform translation.
> > 
> > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> This looks fine, but will need some reworking to rebase on my
> hpt-cleanup patch series.  That might even obsolete the new vhc call.
> 
Yeah the plan is to make this series apply cleanly on your hpt-cleanup.
> > 
> > 
> > ---
> > 
> > V2->V3:
> > - Only add patbe to migration stream if non-zero
> > ---
> >  hw/ppc/spapr.c         | 29 +++++++++++++++++++++++++++++
> >  include/hw/ppc/spapr.h |  1 +
> >  target/ppc/cpu.h       |  1 +
> >  3 files changed, 31 insertions(+)
> > 
> > diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> > index e465d7a..2fbf193 100644
> > --- a/hw/ppc/spapr.c
> > +++ b/hw/ppc/spapr.c
> > @@ -1018,6 +1018,13 @@ static void
> > emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
> >      }
> >  }
> >  
> > +static uint64_t spapr_get_patbe(PPCVirtualHypervisor *vhyp)
> > +{
> > +    sPAPRMachineState *spapr = SPAPR_MACHINE(vhyp);
> > +
> > +    return spapr->patb_entry;
> > +}
> > +
> >  #define HPTE(_table, _i)   (void *)(((uint64_t *)(_table)) + ((_i)
> > * 2))
> >  #define HPTE_VALID(_hpte)  (tswap64(*((uint64_t *)(_hpte))) &
> > HPTE64_V_VALID)
> >  #define HPTE_DIRTY(_hpte)  (tswap64(*((uint64_t *)(_hpte))) &
> > HPTE64_V_HPTE_DIRTY)
> > @@ -1141,6 +1148,8 @@ static void ppc_spapr_reset(void)
> >      /* Check for unknown sysbus devices */
> >      foreach_dynamic_sysbus_device(find_unknown_sysbus_device,
> > NULL);
> >  
> > +    spapr->patb_entry = 0;
> > +
> >      /* Allocate and/or reset the hash page table */
> >      spapr_reallocate_hpt(spapr,
> >                           spapr_hpt_shift_for_ramsize(machine-
> > >maxram_size),
> > @@ -1327,6 +1336,24 @@ static const VMStateDescription
> > vmstate_spapr_ov5_cas = {
> >      },
> >  };
> >  
> > +static bool spapr_patb_entry_needed(void *opaque)
> > +{
> > +    sPAPRMachineState *spapr = opaque;
> > +
> > +    return !!spapr->patb_entry;
> > +}
> > +
> > +static const VMStateDescription vmstate_spapr_patb_entry = {
> > +    .name = "spapr_patb_entry",
> > +    .version_id = 1,
> > +    .minimum_version_id = 1,
> > +    .needed = spapr_patb_entry_needed,
> > +    .fields = (VMStateField[]) {
> > +        VMSTATE_UINT64(patb_entry, sPAPRMachineState),
> > +        VMSTATE_END_OF_LIST()
> > +    },
> > +};
> > +
> >  static const VMStateDescription vmstate_spapr = {
> >      .name = "spapr",
> >      .version_id = 3,
> > @@ -1344,6 +1371,7 @@ static const VMStateDescription vmstate_spapr
> > = {
> >      },
> >      .subsections = (const VMStateDescription*[]) {
> >          &vmstate_spapr_ov5_cas,
> > +        &vmstate_spapr_patb_entry,
> >          NULL
> >      }
> >  };
> > @@ -2733,6 +2761,7 @@ static void
> > spapr_machine_class_init(ObjectClass *oc, void *data)
> >      nc->nmi_monitor_handler = spapr_nmi;
> >      smc->phb_placement = spapr_phb_placement;
> >      vhc->hypercall = emulate_spapr_hypercall;
> > +    vhc->get_patbe = spapr_get_patbe;
> >  }
> >  
> >  static const TypeInfo spapr_machine_info = {
> > diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
> > index a2d8964..c6a929a 100644
> > --- a/include/hw/ppc/spapr.h
> > +++ b/include/hw/ppc/spapr.h
> > @@ -63,6 +63,7 @@ struct sPAPRMachineState {
> >  
> >      void *htab;
> >      uint32_t htab_shift;
> > +    uint64_t patb_entry; /* Process tbl registed in
> > H_REGISTER_PROCESS_TABLE */
> >      hwaddr rma_size;
> >      int vrma_adjust;
> >      ssize_t rtas_size;
> > diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> > index 425e79d..684d632 100644
> > --- a/target/ppc/cpu.h
> > +++ b/target/ppc/cpu.h
> > @@ -1218,6 +1218,7 @@ struct PPCVirtualHypervisor {
> >  struct PPCVirtualHypervisorClass {
> >      InterfaceClass parent;
> >      void (*hypercall)(PPCVirtualHypervisor *vhyp, PowerPCCPU
> > *cpu);
> > +    uint64_t (*get_patbe)(PPCVirtualHypervisor *vhyp);
> >  };
> >  
> >  #define TYPE_PPC_VIRTUAL_HYPERVISOR "ppc-virtual-hypervisor"

Re: [Qemu-devel] [QEMU-PPC] [PATCH V3 07/10] target/ppc/POWER9: Add POWER9 mmu fault handler

[Suraj Jitindar Singh]

On Thu, 2017-02-23 at 15:08 +1100, David Gibson wrote:
> On Mon, Feb 20, 2017 at 03:04:35PM +1100, Suraj Jitindar Singh wrote:
> > 
> > Add a new mmu fault handler for the POWER9 cpu and add it as the
> > handler
> > for the POWER9 cpu definition.
> > 
> > This handler checks if the guest is radix or hash based on the
> > value in the
> > partition table entry and calls the correct fault handler
> > accordingly.
> > 
> > The hash fault handling code has also been updated to check if the
> > partition is using segment tables.
> > 
> > Currently only legacy hash (no segment tables) is supported.
> > 
> > Signed-off-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> > 
> > ---
> > 
> > V2->V3:
> > - error_report on attempt to use segment tables instead of just
> > LOG()
> > - Rename mmu.h -> mmu-book3s-v3.h
> > ---
> >  target/ppc/mmu-book3s-v3.h  | 50
> > +++++++++++++++++++++++++++++++++++++++++++++
> >  target/ppc/mmu-hash64.c     |  8 ++++++++
> >  target/ppc/mmu_helper.c     | 40
> > ++++++++++++++++++++++++++++++++++++
> >  target/ppc/translate_init.c |  3 ++-
> >  4 files changed, 100 insertions(+), 1 deletion(-)
> >  create mode 100644 target/ppc/mmu-book3s-v3.h
> > 
> > diff --git a/target/ppc/mmu-book3s-v3.h b/target/ppc/mmu-book3s-
> > v3.h
> > new file mode 100644
> > index 0000000..9375921
> > --- /dev/null
> > +++ b/target/ppc/mmu-book3s-v3.h
> > @@ -0,0 +1,50 @@
> > +/*
> > + *  PowerPC emulation generic mmu definitions for qemu.
> > + *
> > + *  Copyright (c) 2017 Suraj Jitindar Singh, IBM Corporation
> > + *
> > + * This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU Lesser General Public
> > + * License as published by the Free Software Foundation; either
> > + * version 2 of the License, or (at your option) any later
> > version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> > GNU
> > + * Lesser General Public License for more details.
> > + *
> > + * You should have received a copy of the GNU Lesser General
> > Public
> > + * License along with this library; if not, see <http://www.gnu.or
> > g/licenses/>.
> > + */
> > +
> > +#ifndef MMU_H
> > +#define MMU_H
> > +
> > +#ifndef CONFIG_USER_ONLY
> > +
> > +/* Partition Table Entry Fields */
> > +#define PATBE1_GR 0x8000000000000000
> > +
> > +#ifdef TARGET_PPC64
> > +
> > +static inline bool ppc64_use_proc_tbl(PowerPCCPU *cpu)
> > +{
> > +    return !!(cpu->env.spr[SPR_LPCR] & LPCR_UPRT);
> > +}
> > +
> > +static inline bool ppc64_radix_guest(PowerPCCPU *cpu)
> > +{
> > +    PPCVirtualHypervisorClass *vhc =
> > +        PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp);
> > +
> > +    return !!(vhc->get_patbe(cpu->vhyp) & PATBE1_GR);
> > +}
> > +
> > +int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int
> > rwx,
> > +                              int mmu_idx);
> > +
> > +#endif /* TARGET_PPC64 */
> > +
> > +#endif /* CONFIG_USER_ONLY */
> > +
> > +#endif /* MMU_H */
> > diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
> > index 3e17a9f..a581b50 100644
> > --- a/target/ppc/mmu-hash64.c
> > +++ b/target/ppc/mmu-hash64.c
> > @@ -27,6 +27,7 @@
> >  #include "kvm_ppc.h"
> >  #include "mmu-hash64.h"
> >  #include "exec/log.h"
> > +#include "mmu-book3s-v3.h"
> >  
> >  //#define DEBUG_SLB
> >  
> > @@ -767,6 +768,13 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU
> > *cpu, vaddr eaddr,
> >      /* 2. Translation is on, so look up the SLB */
> >      slb = slb_lookup(cpu, eaddr);
> >      if (!slb) {
> > +        /* No entry found, check if in-memory segment tables are
> > in use */
> > +        if (ppc64_use_proc_tbl(cpu)) {
> > +            /* TODO - Unsupported */
> > +            error_report("Segment Table Support Unimplemented");
> > +            abort();
> > +        }
> > +        /* Segment still not found, generate the appropriate
> > interrupt */
> >          if (rwx == 2) {
> >              cs->exception_index = POWERPC_EXCP_ISEG;
> >              env->error_code = 0;
> > diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
> > index 2911266..527123c 100644
> > --- a/target/ppc/mmu_helper.c
> > +++ b/target/ppc/mmu_helper.c
> > @@ -28,6 +28,8 @@
> >  #include "exec/cpu_ldst.h"
> >  #include "exec/log.h"
> >  #include "helper_regs.h"
> > +#include "qemu/error-report.h"
> > +#include "mmu-book3s-v3.h"
> >  
> >  //#define DEBUG_MMU
> >  //#define DEBUG_BATS
> > @@ -1280,6 +1282,17 @@ void dump_mmu(FILE *f, fprintf_function
> > cpu_fprintf, CPUPPCState *env)
> >      case POWERPC_MMU_2_07a:
> >          dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> >          break;
> > +    case POWERPC_MMU_3_00:
> > +        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> > +            /* TODO - Unsupported */
> > +        } else {
> > +            if (ppc64_use_proc_tbl(ppc_env_get_cpu(env))) {
> > +                /* TODO - Unsupported */
> > +            } else {
> > +                dump_slb(f, cpu_fprintf, ppc_env_get_cpu(env));
> > +                break;
> > +            }
> > +        }
> >  #endif
> >      default:
> >          qemu_log_mask(LOG_UNIMP, "%s: unimplemented\n", __func__);
> > @@ -1421,6 +1434,17 @@ hwaddr ppc_cpu_get_phys_page_debug(CPUState
> > *cs, vaddr addr)
> >      case POWERPC_MMU_2_07:
> >      case POWERPC_MMU_2_07a:
> >          return ppc_hash64_get_phys_page_debug(cpu, addr);
> > +    case POWERPC_MMU_3_00:
> > +        if (ppc64_radix_guest(ppc_env_get_cpu(env))) {
> > +            /* TODO - Unsupported */
> > +        } else {
> > +            if (ppc64_use_proc_tbl(ppc_env_get_cpu(env))) {
> > +                /* TODO - Unsupported */
> > +            } else {
> > +                return ppc_hash64_get_phys_page_debug(cpu, addr);
> > +            }
> I don't think you need the inner if in this case -
> ppc_hash64_get_phys_page_debug() will be basically right for both
> cases, except it will (eventually) need an internal check to consult
> segment tables if they're there.

Good point

> 
> One interesting wrinkle here is that this debug path is exactly a
> case
> where it could be useful to consult the segment tables if the OS
> provides them, even if the actual hardware MMU doesn't use them.

Given a guest won't register one yet this isn't an issue. But would be
nice for debugging when we do.

Thats a job for the next rainy day...

> 
> > 
> > +        }
> > +        break;
> >  #endif
> >  
> >      case POWERPC_MMU_32B:
> > @@ -2907,3 +2931,19 @@ void tlb_fill(CPUState *cs, target_ulong
> > addr, MMUAccessType access_type,
> >                                 retaddr);
> >      }
> >  }
> > +
> > +/*****************************************************************
> > *************/
> > +
> > +/* ISA v3.00 (POWER9) Generic MMU Helpers */
> > +
> > +int ppc64_v3_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int
> > rwx,
> > +                              int mmu_idx)
> > +{
> > +    if (ppc64_radix_guest(cpu)) { /* Guest uses radix */
> > +        /* TODO - Unsupported */
> > +        error_report("Guest Radix Support Unimplemented");
> > +        abort();
> > +    } else { /* Guest uses hash */
> > +        return ppc_hash64_handle_mmu_fault(cpu, eaddr, rwx,
> > mmu_idx);
> > +    }
> > +}
> This can go into a new mmu-books-v3.c, small for now, but it can take
> the radix stuff as well once it gets implemented.
> 

I was putting the radix stuff into mmu-radix64.c. That being said a v3
helper file isn't a bad idea, I'll create and move this to mmu-books-
v3.c.

> > 
> > diff --git a/target/ppc/translate_init.c
> > b/target/ppc/translate_init.c
> > index 32c1619..7661c21 100644
> > --- a/target/ppc/translate_init.c
> > +++ b/target/ppc/translate_init.c
> > @@ -32,6 +32,7 @@
> >  #include "qapi/visitor.h"
> >  #include "hw/qdev-properties.h"
> >  #include "hw/ppc/ppc.h"
> > +#include "mmu-book3s-v3.h"
> >  
> >  //#define PPC_DUMP_CPU
> >  //#define PPC_DEBUG_SPR
> > @@ -8898,7 +8899,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void
> > *data)
> >                      (1ull << MSR_LE);
> >      pcc->mmu_model = POWERPC_MMU_3_00;
> >  #if defined(CONFIG_SOFTMMU)
> > -    pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
> > +    pcc->handle_mmu_fault = ppc64_v3_handle_mmu_fault;
> >      /* segment page size remain the same */
> >      pcc->sps = &POWER7_POWER8_sps;
> >  #endif