From: David Gibson <david@gibson.dropbear.id.au>
To: Richard Henderson <rth@twiddle.net>
Cc: Nikunj Dadhania <nikunj.dadhania@gmail.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
Bharata B Rao <bharata@linux.vnet.ibm.com>
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH v3 03/10] target/ppc: support for 32-bit carry and overflow
Date: Mon, 27 Feb 2017 12:39:49 +1100 [thread overview]
Message-ID: <20170227013949.GO17615@umbus.fritz.box> (raw)
In-Reply-To: <e589819d-ab5e-3c45-0ed8-5783e23ea5d9@twiddle.net>
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On Fri, Feb 24, 2017 at 05:30:23PM +1100, Richard Henderson wrote:
> On 02/24/2017 03:50 PM, David Gibson wrote:
> > Although I guess they'd shrink right down again if we put an
> > env->xer_mask in. Thoughts on that option Richard?
>
> Why would xer_mask shrink the code? I can't see that we'd be able to
> eliminate any code using the mask.
Uh.. I think I was thinking about the qemu code, not the generated
code. It means we could unconditionally and with the xer_mask in some
places, rather than having fiddly conditionals.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2017-02-27 1:46 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-02-22 11:44 [Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15 Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 01/10] target/ppc: move cpu_[read, write]_xer to cpu.c Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 02/10] target/ppc: optimize gen_write_xer() Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 03/10] target/ppc: support for 32-bit carry and overflow Nikunj A Dadhania
2017-02-22 17:17 ` Richard Henderson
2017-02-22 17:20 ` Richard Henderson
2017-02-23 6:40 ` Nikunj A Dadhania
2017-02-23 22:34 ` Richard Henderson
2017-02-23 22:53 ` David Gibson
2017-02-24 0:41 ` [Qemu-devel] [Qemu-ppc] " Nikunj Dadhania
2017-02-24 4:50 ` David Gibson
2017-02-24 6:30 ` Richard Henderson
2017-02-27 1:39 ` David Gibson [this message]
2017-02-23 3:21 ` [Qemu-devel] " David Gibson
2017-02-23 5:09 ` Nikunj A Dadhania
2017-02-23 5:32 ` David Gibson
2017-02-23 7:02 ` Nikunj A Dadhania
2017-02-23 9:29 ` David Gibson
2017-02-23 22:36 ` Richard Henderson
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 04/10] target/ppc: update ca32 in arithmetic add Nikunj A Dadhania
2017-02-22 17:20 ` Richard Henderson
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 05/10] target/ppc: update ca32 in arithmetic substract Nikunj A Dadhania
2017-02-22 17:21 ` Richard Henderson
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 06/10] target/ppc: update overflow flags for add/sub Nikunj A Dadhania
2017-02-22 17:26 ` Richard Henderson
2017-02-23 4:46 ` Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 07/10] target/ppc: use tcg ops for neg instruction Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 08/10] target/ppc: add ov32 flag for multiply low insns Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 09/10] target/ppc: add ov32 flag in divide operations Nikunj A Dadhania
2017-02-22 11:44 ` [Qemu-devel] [PATCH v3 10/10] target/ppc: add mcrxrx instruction Nikunj A Dadhania
2017-02-23 3:27 ` [Qemu-devel] [PATCH v3 00/10] POWER9 TCG enablements - part15 David Gibson
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