From: "Alex Bennée" <alex.bennee@linaro.org>
To: peter.maydell@linaro.org, rth@twiddle.net, pbonzini@redhat.com
Cc: qemu-devel@nongnu.org, mttcg@listserver.greensocs.com,
fred.konrad@greensocs.com, a.rigo@virtualopensystems.com,
cota@braap.org, bobby.prani@gmail.com, nikunj@linux.vnet.ibm.com,
"Alex Bennée" <alex.bennee@linaro.org>,
"open list:ARM" <qemu-arm@nongnu.org>
Subject: [Qemu-devel] [PATCH v2 10/11] target/arm/helper: make it clear the EC field is also in hex
Date: Thu, 2 Mar 2017 19:53:36 +0000 [thread overview]
Message-ID: <20170302195337.31558-11-alex.bennee@linaro.org> (raw)
In-Reply-To: <20170302195337.31558-1-alex.bennee@linaro.org>
..just like the rest of the displayed ESR register. Otherwise people
might scratch their heads if a not obviously hex number is displayed
for the EC field.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
---
target/arm/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 3f4211b572..76b608f0ba 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6857,7 +6857,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
new_el);
if (qemu_loglevel_mask(CPU_LOG_INT)
&& !excp_is_internal(cs->exception_index)) {
- qemu_log_mask(CPU_LOG_INT, "...with ESR %x/0x%" PRIx32 "\n",
+ qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n",
env->exception.syndrome >> ARM_EL_EC_SHIFT,
env->exception.syndrome);
}
--
2.11.0
next prev parent reply other threads:[~2017-03-02 19:53 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-03-02 19:53 [Qemu-devel] [PATCH v2 00/11] MTTCG fixups for 2.9 Alex Bennée
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 01/11] vl/cpus: be smarter with icount and MTTCG Alex Bennée
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 02/11] target/i386/cpu.h: declare TCG_GUEST_DEFAULT_MO Alex Bennée
2017-03-03 19:28 ` Eduardo Habkost
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 03/11] cpus.c: add additional error_report when !TARGET_SUPPORT_MTTCG Alex Bennée
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 04/11] translate: downgrade IRQ BQL asserts to tcg_debug_assert Alex Bennée
2017-03-03 10:08 ` Peter Maydell
2017-03-03 11:05 ` Alex Bennée
2017-03-03 11:19 ` Peter Maydell
2017-03-03 19:35 ` Richard Henderson
2017-03-03 19:47 ` Eric Blake
2017-03-03 19:48 ` Eric Blake
2017-03-03 11:49 ` Paolo Bonzini
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 05/11] translate-all: exit cpu_restore_state early if translating Alex Bennée
2017-03-02 21:46 ` Richard Henderson
2017-03-03 10:03 ` Alex Bennée
2017-03-03 19:50 ` Richard Henderson
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 06/11] sparc/sparc64: grab BQL before calling cpu_check_irqs Alex Bennée
2017-03-03 11:47 ` Paolo Bonzini
2017-03-06 10:28 ` Alex Bennée
2017-03-06 13:22 ` Paolo Bonzini
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 07/11] s390x/misc_helper.c: wrap IO instructions in BQL Alex Bennée
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 08/11] target/xtensa: hold BQL for interrupt processing Alex Bennée
2017-03-07 0:15 ` Max Filippov
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 09/11] target/mips/op_helper: hold BQL before calling cpu_mips_get_count Alex Bennée
2017-03-03 11:18 ` Yongbok Kim
2017-03-03 12:54 ` Alex Bennée
2017-03-03 13:00 ` Yongbok Kim
2017-03-02 19:53 ` Alex Bennée [this message]
2017-03-03 17:07 ` [Qemu-devel] [PATCH v2 10/11] target/arm/helper: make it clear the EC field is also in hex Frederic Konrad
2017-03-03 18:10 ` Peter Maydell
2017-03-02 19:53 ` [Qemu-devel] [PATCH v2 11/11] hw/intc/arm_gic: modernise the DPRINTF Alex Bennée
2017-03-03 17:05 ` Frederic Konrad
2017-03-03 17:09 ` Peter Maydell
2017-03-03 18:09 ` Peter Maydell
2017-03-03 17:38 ` [Qemu-devel] [PATCH v2 00/11] MTTCG fixups for 2.9 Frederic Konrad
2017-03-06 9:43 ` Alex Bennée
2017-03-06 10:45 ` Frederic Konrad
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